Equalization circuit
First Claim
1. A circuit comprising:
- a first differential amplifier having first and second transistors;
a first differential high-pass filter coupled to respective gate terminals of the first and second transistors, wherein a source terminal of the first transistor is coupled to a first input node, and wherein a source terminal of the second transistor is coupled to a second input node;
a second differential amplifier having third and fourth transistors; and
a second differential high-pass filter coupled to respective gate terminals of the third and fourth transistors, wherein a source terminal of the third transistor is coupled to the first input node, and wherein a source terminal of the fourth transistor is coupled to the second input node.
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Accused Products
Abstract
An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.
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Citations
24 Claims
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1. A circuit comprising:
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a first differential amplifier having first and second transistors; a first differential high-pass filter coupled to respective gate terminals of the first and second transistors, wherein a source terminal of the first transistor is coupled to a first input node, and wherein a source terminal of the second transistor is coupled to a second input node; a second differential amplifier having third and fourth transistors; and a second differential high-pass filter coupled to respective gate terminals of the third and fourth transistors, wherein a source terminal of the third transistor is coupled to the first input node, and wherein a source terminal of the fourth transistor is coupled to the second input node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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receiving a first signal at both a source terminal a first transistor of a first differential amplifier and at a source terminal of a third transistor of a second differential amplifier; receiving a second signal at both a source terminal of a second transistor of the first differential amplifier and at a source terminal of a fourth transistor of the second differential amplifier; high-pass filtering, in first and second differential high-pass filters, the first signal to generate filtered versions of the first signal at respective gate terminals of the second and fourth transistors; high-pass filtering, in the first and second differential high-pass filters, the second signal to generate filtered versions of the second signal at respective gate terminals of the first and third transistors; amplifying, in each of the first and second differential amplifiers, a difference between filtered versions of the first and second signals; and generating a differential output signal based on said amplifying. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An apparatus comprising:
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first means for high-pass filtering a differential input signal including a first signal and a second signal; second means for amplifying a difference between the first signal and a high-pass filtered version of the second signal received from said first means and for amplifying a difference between the second signal and a high-pass filtered version of the first signal received from said first means; third means for high-pass filtering the differential input signal; and fourth means for amplifying a difference between the first signal and a high-pass filtered version of the second signal received from said third means and for amplifying a difference between the second signal and a high-pass filtered version of the first signal received from said third means. - View Dependent Claims (17, 18, 19, 20)
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21. A method comprising:
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receiving first and second signals; amplifying, in first and second differential amplifiers, a difference between filtered versions of the first and second signals; generating, based on said amplifying, a differential output having first and second full-rail digital output signals on first and second output paths, respectively; providing the first full-rail digital output signal as continuous time feedback to an input of the second output path; and providing the second full-rail digital output signal as continuous time feedback to an input of the first output path. - View Dependent Claims (22, 23, 24)
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Specification