Semiconductor signal processing device
First Claim
1. A semiconductor signal processing device comprising:
- a plurality of unit operator cells arranged in rows and columns and being divided into operation unit blocks in a row direction, each for storing data in a nonvolatile manner and passing a current of a different amount according to the storage data;
a write circuit for expanding each bit of multi-bit numerical data to a number of bits corresponding to a bit position in the numerical data to produce internal write data in each operation unit block, for concurrently selecting unit operator cells in the operation unit block, and for concurrently writing bits of said internal write data corresponding to said multi-bit numerical data in corresponding unit operator cells in the operation unit block;
a plurality of global read data lines arranged corresponding to the columns of said plurality of unit operator cells;
a read circuit for concurrently selecting the unit operator cells of a plurality of rows in said plurality of unit operator cells in data reading, and for passing a current corresponding to data stored in each selected selection unit operator cell through a corresponding global read data line; and
a conversion circuit for adding currents supplied through the global read data lines in an analog manner in each operation unit block, and converting a result of the adding into a digital signal.
1 Assignment
0 Petitions
Accused Products
Abstract
A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.
384 Citations
10 Claims
-
1. A semiconductor signal processing device comprising:
-
a plurality of unit operator cells arranged in rows and columns and being divided into operation unit blocks in a row direction, each for storing data in a nonvolatile manner and passing a current of a different amount according to the storage data; a write circuit for expanding each bit of multi-bit numerical data to a number of bits corresponding to a bit position in the numerical data to produce internal write data in each operation unit block, for concurrently selecting unit operator cells in the operation unit block, and for concurrently writing bits of said internal write data corresponding to said multi-bit numerical data in corresponding unit operator cells in the operation unit block; a plurality of global read data lines arranged corresponding to the columns of said plurality of unit operator cells; a read circuit for concurrently selecting the unit operator cells of a plurality of rows in said plurality of unit operator cells in data reading, and for passing a current corresponding to data stored in each selected selection unit operator cell through a corresponding global read data line; and a conversion circuit for adding currents supplied through the global read data lines in an analog manner in each operation unit block, and converting a result of the adding into a digital signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A semiconductor signal processing device comprising:
-
a plurality of unit operator cells arranged in rows and columns, each for storing data in a nonvolatile manner, each unit operator cell including a storage element causing a current flow of an amount depending on storage data, said plurality of unit operator cells being divided into a plurality of operation unit blocks in a row direction and being divided into a plurality of sub-array blocks in a column direction, a bit position of multi-bit numerical data of an operation target being previously allocated to each of said plurality of sub-array blocks; a write circuit for concurrently writing corresponding bits of said multi-bit numerical data in sub-array blocks previously allocated according to weights of bit positions of the corresponding bits in said multi-bit numerical data in said plurality of sub-array blocks, said write circuit writing data of an identical bit position in a set of plurality of operation target data in the unit operator cells being aligned in said column direction in one sub-array block; a plurality of global read data lines arranged corresponding to the operation unit blocks of the unit operator cells and commonly to the sub-array blocks of each respective operation unit block; a read circuit for passing a current through a corresponding global read line according to data stored in a selected unit operator cell in each sub-array block in which said set of operation target data is stored, said read circuit connecting the sub-array block and said corresponding global read data line for a time period being set according to said bit position allocated to each sub-array block; and a conversion circuit for adding the currents passed through the corresponding global read data line in the operation unit block in analog manner, to convert a result of the adding into a digital signal. - View Dependent Claims (9, 10)
-
Specification