Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same

• US 8,274,849 B2
• Filed: 05/20/2011
• Issued: 09/25/2012
• Est. Priority Date: 04/04/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bauser, Philippe
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/112,526
• Publication Number:
  US 20110216609A1
• Time in Patent Office: 494 Days
• Field of Search: 365/174, 365/189.15, 365/189.07, 365/189.09, 365/203, 365/204, 365/233.17, 365/242
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.

Claims

1. A method of reading a memory cell comprising:

applying read control signals to a selected memory cell of a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell of the plurality of memory cells comprises an electrically floating body transistor including a body region which is electrically floating and configured to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state representative of a second charge in the body region of the electrically floating body transistor;

generating a current on a bit line coupled to the selected memory cell in response to the read control signals, wherein the current is representative of a data state stored in the selected memory cell;

controlling the generated current on the bit line by the selected memory cell by sinking or sourcing at least a portion of the current on the bit line generated by the selected memory cell;

sensing a first voltage potential on the bit line to determine the data state stored in the selected memory cell based at least in part on a reference signal and the first voltage potential on the bit line, wherein sinking or sourcing at least a portion of the current on the bit line generated by the selected memory cell includes sinking or sourcing a substantial portion of the current on the bit line generated by the selected memory cell after sensing the first voltage potential on the bit line; and

outputting a data state signal which is representative of the data state stored in the selected memory cell.

2. The method of claim 1, wherein controlling the generated current on the bit line comprises sensing a second voltage potential on the bit line.

3. The method of claim 2, wherein the second voltage potential on the bit line has an amplitude based at least in part on an amount of the current generated on the bit line.

4. The method of claim 3, wherein controlling the generated current on the bit line further comprises comparing the second voltage potential on the bit line to a threshold voltage potential.

5. The method of claim 4, wherein controlling the generated current on the bit line further comprises providing an electrical path to sink the at least a portion of the current on the bit line generated by the selected memory cell if the second voltage potential on the bit line exceeds the threshold voltage potential.

6. The method of claim 4, wherein controlling the generated current on the bit line further comprises providing an electrical path to sink the at least a portion of the current on the bit line generated by the selected memory cell if the second voltage potential on the bit line equals to the threshold voltage potential.

7. The method of claim 4, wherein controlling the generated current on the bit line further comprises providing an electrical path to source the at least a portion of the current on the bit line generated by the selected memory cell if the second voltage potential on the bit line is less than the threshold voltage potential.

8. The method of claim 1, wherein sinking or sourcing at least a portion of the current on the bit line further comprises applying a regulation current that is substantially equal to the at least a portion of the current on the bit line.

9. The method of claim 8, wherein the regulation current is a constant current.

10. The method of claim 1, further comprising applying a precharge voltage potential to the bit line in order to establish a predetermined condition on the bit line.

11. The method of claim 10, wherein the precharge voltage potential is substantially equal to ground or common.

12. The method of claim 11, wherein the read control signals are applied to the selected memory cell prior to completing the establishment of the predetermined condition on the bit line.

13. The method of claim 1, wherein applying read control signals to the selected memory cell comprises applying a first selection signal via a word line to a gate region of the selected memory cell.

14. The method of claim 13, wherein applying read control signals to the selected memory cell further comprises applying a second selection signal via a source line to a source region of the selected memory cell.

15. The method of claim 1, wherein the data state stored in the selected memory cell is determined by comparing the first voltage potential with a voltage potential of the reference signal.

16. The method of claim 15, wherein a logic high is stored in the selected memory cell if the first voltage potential equals or exceeds the voltage potential of the reference signal.

17. The method of claim 15, wherein a logic low is stored in the selected memory cell if the first voltage potential is less than the voltage potential of the reference signal.

18. At least one non-transitory processor readable storage medium storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 1.