Multi-mode transmitter

• US 8,275,027 B2
• Filed: 05/08/2008
• Issued: 09/25/2012
• Est. Priority Date: 06/12/2007
• Status: Expired due to Fees

• Current Assignee: Rambus Inc., Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Rambus Inc., Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Abbasfar, Aliazam, Amirkhany, Amir
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): NEFF, MICHAEL R
• Application Number:
  US12/117,680
• Publication Number:
  US 20080310491A1
• Time in Patent Office: 1,601 Days
• Field of Search: 375/230, 375/295
• US Class Current: 375/230
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453

Abstract

A multi-mode transmitter within an integrated circuit device. The multi-mode transmitter transmits a first data sequence in a baseband signal when a first transmission mode is enabled, and transmits the first data sequence in a multi-band signal when a second transmission mode is enabled.

Claims

1. An integrated circuit device comprising:

an output node including a pad for coupling to a wired transmission line;

a plurality of equalizer circuits including coefficient storage circuits for storing selected tap coefficients; and

wireline transmission circuitry coupled to the output node and to output via the output node for wireline transmission along the wired transmission line either a baseband signal or a multi-band signal based on the selected tap coefficients.

2. The integrated circuit device of claim 1 wherein the wireline transmission circuitry comprises a multi-band transmitter, a baseband transmitter and a multiplexer having inputs coupled to respective outputs of the multi-band transmitter and baseband transmitter, the multiplexer having an output coupled to the output node.

3. The integrated circuit device of claim 2 further comprising a mode selection register to output to the multiplexer a logic signal that represents the transmission mode selection.

4. The integrated circuit device of claim 1 wherein the wireline transmission circuitry comprises:

a serial-to-parallel converter to generate a plurality of data substreams from an input data stream;

a plurality of equalizer circuits each coupled to receive a respective one of the data substreams and having a respective coefficient storage circuit for storage of coefficients to be multiplied with values in the respective one of the data substreams; and

a summing element to combine the outputs of the plurality of equalizer circuits to generate an output signal to be transmitted via the output node.

5. The integrated circuit device of claim 4 wherein the summing element is a node at which outputs of the plurality of equalizer circuits are coupled to one another to effect a wired summation.

6. The integrated circuit device of claim 4 wherein, when a first set of coefficients is stored within the coefficient storage circuits of the plurality of equalizer circuits to effect a first mode selection, the transmitter is enabled to convey a transmit data sequence in a baseband transmission, and, when a second set of coefficients is stored within the coefficient storage circuits of the plurality of equalizer circuits to effect a second mode selection, the transmitter is enabled to convey the transmit data sequence in a multi-band transmission.

7. The integrated circuit device of claim 6 wherein, when a third set of coefficients is stored within the coefficient storage circuits of the plurality of equalizer circuits to effect a third mode selection, the transmitter is enabled to convey a transmit data sequence in a multi-PAM (Pulse Amplitude Modulation) transmission in which each transmitted symbol conveys more than a single bit of the transmit data sequence.

8. The integrated circuit device of claim 4 wherein, a baseband output signal is generated by coefficients within a coefficient storage circuit that corresponds to a first one of the data substreams that are a time displaced version of coefficients within a coefficient storage circuit that corresponds to a second one of the data substreams.

9. The integrated circuit device of claim 4 wherein, a multi-band output signal is generated by coefficients within a coefficient storage circuit that corresponds to a first one of the data substreams effect a first filtering operation, and by coefficients with that selects a be a time displaced version of the coefficients within a coefficient storage circuit that corresponds to a second one of the data substreams effect a second filtering operation, the first filtering operation yielding an output signal component that is spectrally offset from an output signal component yielded by the second filtering operation.

10. A method comprising:

equalizing in a plurality of equalizers including coefficient storage for storing selected tap coefficients;

transmitting a first data sequence in a baseband signal along a wired transmission line when a first transmission mode is enabled based on the selected tap coefficients; and

transmitting the first data sequence in a multi-band signal along the wired transmission line when a second transmission mode is enabled based on the selected tap coefficients.

11. The method of claim 10 further comprising:

switchably coupling a baseband transmitter to an output node of an integrated circuit device when the first transmission mode is enabled, and

switchably coupling a multi-band transmitter to the output node of the integrated circuit device when the second transmission mode is enabled.

12. The method of claim 10 further comprising:

storing a first plurality of equalizer coefficients within a plurality of equalizers of a transmission circuit to effect baseband signal generation when the first transmission mode is enabled; and

storing a second plurality of equalizer coefficients within the plurality of equalizers of the transmission circuit to effect multi-band signal generation when the second transmission mode is enabled.

13. The method of claim 12 further comprising storing a third plurality of equalizer coefficients within the plurality of equalizers of the transmission circuit when a third transmission mode is enabled, the transmitter being enabled, in the third transmission mode, to convey the first data sequence in a multi-PAM (Pulse Amplitude Modulation) transmission in which each transmitted symbol conveys more than a single bit of the first data sequence.

14. The method of claim 12 wherein transmitting the first data sequence in a baseband signal comprises:

converting the first data sequence from a single serial stream of data values to a plurality of parallel data substreams; and

filtering each of the parallel data substreams in a respective one of the plurality of equalizers after storing the first plurality of equalizer coefficients therein.

15. The method of claim 12 wherein transmitting the first data sequence in a multi-band signal comprises:

converting the first data sequence from a single serial stream of data values to a plurality of parallel data substreams; and

filtering each of the parallel data substreams in a respective one of the plurality of equalizers after storing the second plurality of equalizer coefficients therein.

16. An integrated circuit device comprising:

means for equalizing with a plurality of equalizers including coefficient storage for storing selected tap coefficients;

means for wireline transmitting a first data sequence in a baseband signal when a first transmission mode is enabled based on the selected tap coefficients; and

means for wireline transmitting the first data sequence in a multi-band signal when a second transmission mode is enabled based on the selected tap coefficients.

17. The integrated circuit device of claim 16 wherein the means for wireline transmitting the first data sequence in a baseband signal comprises a baseband transmitter having an output switchably coupled to an output node of the integrated circuit device, and wherein the means for wireline transmitting the first data sequence in a multi-band signal comprises a multi-band transmitter having an output switchably coupled to the output node of the integrated circuit device.

18. The integrated circuit device of claim 16 further comprising means for storing a first plurality of equalizer coefficients within a plurality of equalizers of a transmission circuit to effect baseband signal generation when the first transmission mode is enabled, and for storing a second plurality of equalizer coefficients within the plurality of equalizers of the transmission circuit to effect multi-band signal generation when the second transmission mode is enabled.

19. The integrated circuit device of claim 18 wherein the means for storing the first plurality of equalizer coefficients and for storing the second plurality of equalizer coefficients comprises means for storing a third plurality of equalizer coefficients to effect a multi-PAM (Pulse Amplitude Modulation) transmission in which each transmitted symbol conveys more than a singe bit of the first data sequence.

20. A manufacture comprising one or more non-transitory computer-readable media, the computer-readable media having information embodied therein that describes a physical implementation of an integrated circuit device, the information including descriptions of:

a plurality of equalizer circuits including coefficient storage circuits for storing selected tap coefficients; and

a multi-band transmitter,

a baseband transmitter; and

a multiplexer having inputs coupled to respective outputs of the multi-band transmitter and baseband transmitter, the multiplexer having an output selected based on the selected tap coefficients coupled to an output node of an integrated circuit device, the output node including a pad for coupling to a wired transmission line.

21. The manufacture comprising the one or more non-transitory computer-readable media of claim 20, wherein the information further comprises descriptions of:

a serial-to-parallel converter to generate a plurality of data substreams from an input data stream;

a plurality of equalizer circuits each coupled to receive a respective one of the data substreams and having a respective coefficient storage circuit for storage of coefficients to be multiplied with values in the respective one of the data substreams; and

a summing element to combine the outputs of the plurality of equalizer circuits to generate an output signal to be transmitted via the output node of the integrated circuit device.