Source packet bridge

• US 8,275,910 B1
• Filed: 07/02/2003
• Issued: 09/25/2012
• Est. Priority Date: 07/02/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hauck, Jerrold V.
• Primary Examiner(s): Shaw, Peling
• Assistant Examiner(s): Cloud, Joiya M
• Application Number:
  US10/613,867
• Time in Patent Office: 3,373 Days
• Field of Search: 709/249, 709/231
• US Class Current: 709/249
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052

Abstract

A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interlace between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream.

Claims

1. A method of implementing a source packet bridge on a network of nodes, comprising:

providing a node having a first port, the first port having a first time base, a second port, the second port connected to a second bus having a second time base, and an internal interface between the first port and the second port, wherein the first port is connected to a first bus, the first bus having a first cycletimer value, and wherein the second port is connected to a second bus, the second bus having a second cycletimer value that has a time base different than that of the first cycletimer value;

receiving a data stream containing a first set of packets over the first port and extracting a timestamp from a packet, wherein each packet of said first set of packets comprises a plurality of data blocks;

dynamically evaluating a difference between the first cycletimer value and the second cycletimer value;

adjusting the timestamp by adding to it said difference and a latency value;

said latency value being greater than or equal to a predetermined delay value;

said delay value calculated with respect to said second time base;

accumulating data blocks from said first set of packets within an internal (first in first out) FIFO;

packetizing and transmitting a second set of packets over the second port, said second set of packets comprising data blocks retrieved from the internal FIFO; and

wherein the internal FIFO enables packing of a first packet of the second set of packets with data blocks accumulated over a plurality of the first set of packets.

2. The method of claim 1, wherein the data stream received over the first port is an isochronous data stream that is compliant with the IEEE 61883 Transport Protocol.

3. The method of claim 1, wherein the rate of packets received over the first port is substantially equivalent to the rate of packets transmitted over the second port.

4. The method of claim 1, wherein the rate of packets received over the first port is substantially different to the rate of packets transmitted over the second port.

5. The method of claim 1, wherein the packets received over the first port are compliant with an IEEE 1394 high speed bus.

6. The method of claim 1, wherein the packets transmitted over the second port are compliant with an IEEE 1394 high speed bus.

7. The method of claim 1, wherein the packets transmitted over the second port contain audio/visual (A/V) content.

8. A system to re-packetize incoming data encapsulated within one or more packets, the system comprising:

a first bus operating at a first clock frequency to receive one or more incoming data;

a second bus operating at a second clock frequency, different than the first clock frequency, to transmit a modified version of the incoming data as output data; and

a latency adjustment module that comprises logic configured to;

accumulate data blocks from the one or more incoming data within an internal (first in first out) FIFO;

where the internal FIFO is configured to pack a first packet of the output data with data blocks accumulated from the one or more incoming data;

transmit the output data over the second bus;

wherein the output data comprises an outgoing packing density, the incoming data comprises an incoming packing density, and the incoming packet density and outgoing packing density are substantially different; and

wherein the latency adjustment module is further configured to compensate for the substantial difference between the outgoing packing density and the incoming packing density to maintain a substantially constant bandwidth into and out of the system.

9. The system of claim 8, wherein the one or more incoming data received over the first port is compliant with the IEEE 61883 Transport Protocol.

10. The system of claim 8, wherein the one or more incoming data received over the first port is isochronous.

11. The system of claim 8, where the substantial difference comprises a difference in a number of packets received via the first bus and a number of packets transmitted via the second bus.

12. The system of claim 11, wherein the packets received over the first bus are compliant with an IEEE 1394 high speed bus.

13. The system of claim 11, wherein the packets transmitted over the second bus are compliant with an IEEE 1394 high speed bus.

14. The method of claim 11, wherein the system maintains a bounded clock variance.

15. A source bridge apparatus, comprising:

a first bus operating at a first clock frequency to receive one or more incoming data;

a second bus operating at a second clock frequency;

an internal (first in first out) FIFO, where the internal FIFO is configured to pack a first packet of an output data with data blocks accumulated from the one or more incoming data;

a processor; and

a computer readable non-transitory storage medium with at least one computer program stored thereon, the at least one computer program configured to, when executed on the processor;

accumulate data blocks from the one or more incoming data within the internal FIFO;

determine an outgoing packing density and an incoming packing density; and

when the incoming packet density and outgoing packing density are substantially different, compensate for the substantial difference between the outgoing packing density and the incoming packing density to maintain a substantially constant bandwidth into and out of the source bridge apparatus.

16. The source bridge apparatus of claim 15, wherein the outgoing packing density is expressed in data blocks per isochronous interval.

17. The source bridge apparatus of claim 15, wherein the incoming packing density is expressed in data blocks per isochronous interval.

18. The source bridge apparatus of claim 15, wherein the first bus is compliant with an IEEE 1394 standard.

19. The source bridge apparatus of claim 15, wherein the second bus is compliant with an IEEE 1394 standard.

21. The method of claim 15, wherein the application interface is associated with an audio/visual (A/V) application.

20. A method, comprising:

receiving data packets on a first bus having a first time base;

accumulating the received data packets within an internal (first in first out) FIFO;

recreating the data packets on the internal FIFO in accordance with the first time base, the internal FIFO being adapted to emulate an application interface associated with a coder/decoder;

sampling the data packets from the internal FIFO at a second bus, the second bus being capable of transmitting a full or partially-full packet upon receiving an empty or partially packed isochronous packet from the first bus and maintaining a fixed latency delivery model of the IEEE 61883 transport protocol;

stamping with a timestamp associated with a second time base the data packets received from the internal FIFO in response to performance of a dynamic evaluation, the dynamic evaluation comprising an evaluation of each packet of the data packets on the second bus prior to the stamping; and

packetizing the stamped and sampled data packets utilizing an IEEE 61883-compliant transport protocol to conform with a minimum and maximum number of data blocks per isochronous period, the minimum and maximum number of data blocks being adapted to be responsive to a number of data blocks received at the first bus, and the maximum number of data blocks that can be packed together;

wherein the second bus does not receive synchronization commands from the first bus.