Load reduction system and method for DIMM-based memory systems

• US 8,275,936 B1
• Filed: 09/21/2009
• Issued: 09/25/2012
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Inphi Corporation
• Inventors: Haywood, Christopher, Raghavan, Gopal, Xu, Chao
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US12/563,308
• Time in Patent Office: 1,100 Days
• Field of Search: 711/5, 711/105, 711/154, 365/189.05
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1657 Access to multiple memories

Abstract

A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.

Claims

1. A memory system which includes a plurality of DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer and select/distribute a certain subset of data bytes being written to or read from said plurality of DIMMs, said system organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes that are not routed to all DIMMs and stored in a given distributed rank consisting of RAM chips on several DIMMs, comprising:

a host controller;

a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots; and

wiring which provides byte lanes between said host controller and said plurality of DIMM slots via which data is written to and read from said DIMMs such that individual bytes may be read or written to RAM chips of different DIMMs as a function of said byte lane routing;

said system arranged such that the RAM chips that constitute a given rank are re-mapped across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present.

2. The system of claim 1, wherein said system is arranged such that any given byte lane is wired to no more than two of said DIMM slots such that the loading on said byte lane is limited to no more than the electrical loads associated with one or two of said memory buffer circuits.

3. The system of claim 1, wherein said RAM chips comprise DRAM chips.

4. The system of claim 1, wherein a data word comprises 64 or 72 bits which are conveyed via eight or nine 8-bit byte lanes or via 16 or 18 4-bit byte lanes.

5. The system of claim 1, further comprising a command/address bus which conveys command and address data between said host controller and said DIMMs, said memory buffer circuits further arranged to receive and buffer said command and address data.

6. The system of claim 1, wherein said memory buffer circuits are arranged to route data bytes to respective RAM chips in accordance with said re-mapping.

7. The system of claim 1, wherein one or more of said DIMMs contains multiple ranks.

8. The system of claim 1, wherein said memory system includes two, three or four DIMM slots and said host controller is arranged to write data to and read data from DIMMs plugged into said two, three or four DIMM slots.

9. The system of claim 1, wherein said memory system includes four DIMM slots, said system arranged such that at least two of said DIMM slots must be populated with a DIMM.

10. The system of claim 1, wherein said host controller is mounted to a motherboard to which said DIMM slots are also mounted, said wiring comprising interconnection traces on said motherboard between said host controller and said DIMM slots.

12. The system of claim 1, wherein said system has x ranks which are enabled with respective channel select (CS) signals which are nominally provided by said host controller, said system and memory buffer circuits arranged such that said memory buffer circuits 1) receive y address signals from said host controller in lieu of said CS signals, such that 2^y≧

x,

     2) decode said address signals, and

     3) provide said CS signals as needed to implement said re-mapping.

11. A memory system which includes one or more DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer data bytes being written to or read from said DIMM, said system nominally organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes and stored in a given rank consisting of parallel-connected RAM chips on a given DIMM, comprising:

a host controller;

a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots; and

wiring which provides byte lanes between said host controller and said DIMM slots via which data is written to and read from said DIMMs;

said system arranged such that the RAM chips that constitute a given rank are re-mapped across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present;

wherein said host controller has m byte lanes and said system is arranged such that said re-mapping scheme requires a total of n connections between said host controller'"'"'s byte lanes and said DIMM slots, further comprising a byte lane switch having m I/O ports connected to said host controller'"'"'s m byte lanes and n I/O ports connected to said DIMM slots, said switch arranged to buffer data between said host controller'"'"'s byte lanes and said DIMM slots such that the loading on each of said host controller'"'"'s byte lanes is limited to no more than the one electrical load associated with said byte lane switch.

13. A method of storing data in a memory system which includes a plurality of DIMM slots adapted to receive respective DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer and select/distribute a certain subset of data bytes being written to or read from said plurality of DIMMs, said system organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes that are not routed to all DIMMs and stored in a given distributed rank consisting of RAM chips on several DIMMs, comprising:

providing a host controller;

providing a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots;

providing wiring which provides byte lanes between said host controller and said plurality of DIMM slots via which data is written to and read from said DIMMs such that individual bytes may be read or written to RAM chips of different DIMMs as a function of said byte lane routing; and

re-mapping the RAM chips that constitute a given rank across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present.