Non-volatile memory based reliability and availability mechanisms for a computing device

• US 8,276,018 B2
• Filed: 04/30/2010
• Issued: 09/25/2012
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kursun, Eren, Emma, Philip G., Gates, Stephen M.
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Manoskey, Joseph D
• Application Number:
  US12/771,293
• Publication Number:
  US 20110271141A1
• Time in Patent Office: 879 Days
• Field of Search: 714/6.1, 714/6.31, 714/10, 714/15, 714/20, 714/23, 714/27, 714/30, 714/33, 714/37, 714/39, 714/45, 714/47.1, 714/47.2, 714/47.3
• US Class Current: 714/10
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.

Claims

1. A method, in a data processing system, for storing selected reliability information in an on-chip non-volatile storage device, comprising:

collecting, by an on-chip reliability controller coupled to one or more on-chip resources of a microprocessor chip, raw reliability information from the one or more on-chip resources of the microprocessor chip;

analyzing, by the on-chip reliability controller, the raw reliability information to identify selected reliability information for the one or more on-chip resources of the microprocessor chip; and

storing the selected reliability information in the on-chip non-volatile storage device, wherein the on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device in the event of an overall failure of the microprocessor chip.

2. The method of claim 1, wherein the on-chip reliability controller collects the raw reliability information from at least one of one or more hardware sensors or one or more hardware counters associated with the one or more on-chip resources of the microprocessor chip.

3. The method of claim 1, wherein analyzing the raw reliability information to identify selected reliability information for the one or more on-chip resources of the microprocessor chip comprises:

generating a reliability profile in the on-chip reliability controller that stores reliability information identifying at least a subset of the on-chip resources, associated failures of the subset of on-chip resources, and a criticality level of the associated failures of the subset of on-chip resources; and

filtering the reliability profile based on at least the criticality level of the associated failures of the subset of on-chip resources.

4. The method of claim 3, wherein the reliability profile is generated by:

comparing the raw reliability information to one or more threshold conditions;

determining if the one or more threshold conditions are violated by the raw reliability information; and

in response to a determination that the one or more threshold conditions are violated by the raw reliability information, writing an entry to the reliability profile identifying a on-chip resource associated with the raw reliability information, a type of failure associated with the determination, and a criticality level of the failure associated with the determination.

5. The method of claim 4, wherein the one or more threshold conditions are stored in the on-chip non-volatile storage device and are accessible to the on-chip reliability controller.

6. The method of claim 1, further comprising:

storing a history of selected reliability information in the on-chip non-volatile storage device, wherein the history of selected reliability information comprises selected reliability information for the on-chip resources of the microprocessor chip for a previous period of time.

7. The method of claim 1, wherein the on-chip non-volatile storage device is one of a bank of eFuses, an electrically erasable programmable read only memory (EEPROM), a magnetoresistive random access memory, a resistive random access memory (RRAM), or a phase change memory.

8. The method of claim 1, wherein the on-chip non-volatile storage device stores the critical reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power.

9. The method of claim 1, further comprising:

accessing, by an off-chip device, the on-chip non-volatile storage device in response to a failure of the microprocessor chip;

analyzing the selected reliability information in the on-chip non-volatile storage device to identify new start-up configuration settings for the microprocessor chip; and

attempting a restart of the microprocessor chip using the new start-up configuration settings for the microprocessor chip.

10. The method of claim 9, wherein attempting a restart of the microprocessor chip using the new start-up configuration settings for the microprocessor chip comprises:

writing, by the off-chip device, the new start-up configuration settings to the on-chip non-volatile storage device;

accessing, by the on-chip reliability controller, the new start-up configuration settings stored in the on-chip non-volatile storage device; and

restarting, by the on-chip reliability controller, the microprocessor chip using the new start-up configuration settings accessed from the on-chip non-volatile storage device.

11. An apparatus, comprising:

at least one on-chip resource of a microprocessor chip;

an on-chip reliability controller coupled to the at least one on-chip resource of the microprocessor chip; and

an on-chip non-volatile storage device coupled to the on-chip reliability controller, wherein the on-chip reliability controller;

collects raw reliability information from the one or more on-chip resources of the microprocessor chip;

analyzes the raw reliability information to identify selected reliability information for the one or more on-chip resources of the microprocessor chip; and

stores the selected reliability information in the on-chip non-volatile storage device, wherein the on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the chip.

12. The apparatus of claim 11, further comprising:

one or more hardware sensors coupled to the one or more on-chip resources of the microprocessor chip; and

one or more hardware counters associated with the one or more on-chip resources of the microprocessor chip, wherein the on-chip reliability controller collects the raw reliability information from the one or more hardware sensors and one or more hardware counters.

13. The apparatus of claim 11, wherein the on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more on-chip resources of the microprocessor chip by:

generating a reliability profile in the on-chip reliability controller that stores reliability information identifying at least a subset of the on-chip resources, associated failures of the subset of on-chip resources, and a criticality level of the associated failures of the subset of on-chip resources; and

filtering the reliability profile based on at least the criticality level of the associated failures of the subset of on-chip resources.

14. The apparatus of claim 13, wherein on-chip reliability controller generates the reliability profile by:

comparing the raw reliability information to one or more threshold conditions;

determining if the one or more threshold conditions are violated by the raw reliability information; and

in response to a determination that the one or more threshold conditions are violated by the raw reliability information, writing an entry to the reliability profile identifying a resource associated with the raw reliability information, a type of failure associated with the determination, and a criticality level of the failure associated with the determination.

15. The apparatus of claim 14, wherein the one or more threshold conditions are stored in the on-chip non-volatile storage device and are accessible to the on-chip reliability controller.

16. The apparatus of claim 11, wherein the on-chip non-volatile storage device further stores a history of selected reliability information in the on-chip non-volatile storage device, wherein the history of selected reliability information comprises selected reliability information for the resources of the chip for a previous period of time.

17. The apparatus of claim 11, wherein the on-chip non-volatile storage device is one of a bank of eFuses, an electrically erasable programmable read only memory (EEPROM), a magnetoresistive random access memory, a resistive random access memory (RRAM), or a phase change memory.

18. The apparatus of claim 11, wherein the on-chip non-volatile storage device stores the critical reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power.

19. The apparatus of claim 11, further comprising:

an interface through which an off-chip device accesses the on-chip non-volatile storage device, and wherein the off-chip device;

accesses the on-chip non-volatile storage device, via the interface, in response to a failure of the chip;

analyzes the selected reliability information in the on-chip non-volatile storage device to identify new start-up configuration settings for the chip; and

attempts a restart of the chip using the new start-up configuration settings for the chip.

20. The apparatus of claim 19, wherein the off-chip device attempts a restart of the chip using the new start-up configuration settings for the chip by writing;

via the interface, the new start-up configuration settings to the on-chip non-volatile storage device, and wherein the on-chip reliability controller;

accesses the new start-up configuration settings stored in the on-chip non-volatile storage device; and

restarts the chip using the new start-up configuration settings accessed from the on-chip non-volatile storage device.