Automatic positioning of gate array circuits in an integrated circuit design

• US 8,276,105 B2
• Filed: 09/18/2009
• Issued: 09/25/2012
• Est. Priority Date: 09/18/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Keinert, Joachim, Lamb, Douglass T., Lewis, David W., Ramji, Shyam
• Primary Examiner(s): Do, Thaun
• Application Number:
  US12/563,021
• Publication Number:
  US 20110072407A1
• Time in Patent Office: 1,103 Days
• Field of Search: 716/55, 716/119, 716/139
• US Class Current: 716/55
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.

Claims

1. An automated method for positioning gate array circuits in an integrated circuit design, the method comprising:

providing an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells;

receiving a gate array logic element design to be placed in the integrated circuit design;

automatically determining an initial placement position for the gate array logic element at any position between adjacent logic cells in alignment with the single step size grid based on at least one circuit design consideration;

after automatically determining the initial placement position for the gate array logic element;

when the initial placement position is not aligned with the least common multiple step size grid, automatically positioning the gate array logic element in a final position aligned with the least common multiple step size grid, wherein the final position is different from the initial position by a multiple of single step size grid cells; and

automatically positioning gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element.

2. The method of claim 1, wherein the step of automatically positioning gate array fill circuits comprises:

automatically filling the space between adjacent logic cells in the initial integrated circuit design with one or more gate array fill circuits aligned with the least common multiple step size grid to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits.

3. The method of claim 2, wherein the step of automatically determining the gate array logic element comprises:

identifying one or more contiguous gate array fill circuits in the initial integrated circuit design having a contiguous circuit area corresponding to a circuit area requirement of the gate array logic element; and

replacing the identified contiguous gate array fill circuits with the gate array logic element in the integrated circuit design.

4. The method of claim 1, wherein the providing step comprises:

positioning a plurality of logic cells aligned on the single step size grid in the integrated circuit design using an electronic design automation tool; and

positioning one or more gate array fill circuits in the space between the adjacent logic cells and aligned with the single step size grid beginning with a single step size grid location immediately adjacent to at least one of the adjacent logic cells to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits and thereby to define the least common multiple step size grid between the adjacent logic cells.

5. The method of claim 1, wherein the step of determining an initial placement position of the gate array logic element comprises:

making available for the initial placement position any position between adjacent logic cells in alignment with the single step size grid in which one or more gate array fill circuits are positioned in the initial integrated circuit design.

6. The method of claim 1, wherein the at least one circuit design consideration includes circuit timing considerations.

7. A computer program product including a computer readable storage device having stored thereon computer program instructions for controlling a data processing system to automatically position gate array circuits in an integrated circuit design, comprising:

computer program instructions stored on the computer readable storage medium to receive an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells;

computer program instructions stored on the computer readable storage medium to receive a gate array logic element design to be placed in the integrated circuit design;

computer program instructions stored on the computer readable storage medium to automatically determine an initial placement position for the gate array logic element at any position between adjacent logic cells in alignment with the single step size grid based on at least one circuit design consideration;

after automatically determining the initial placement position for the gate array logic element;

when the initial placement position is not aligned with the least common multiple step size grid, computer program instructions stored on the computer readable storage medium to automatically position the gate array logic element in a final position aligned with the least common multiple step size grid, wherein the final position is different from the initial position by a multiple of single step size grid cells; and

computer program instructions stored on the computer readable storage medium to position automatically gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element.

8. The computer program product of claim 7, wherein the instructions to position automatically gate array fill circuits comprises computer program instructions stored on the computer readable storage medium to:

automatically fill the space between adjacent logic cells in the initial integrated circuit design with one or more gate array fill circuits aligned with the least common multiple step size grid to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits.

9. The computer program product of claim 8, wherein the instructions to automatically determine the gate array logic element comprises computer program instructions stored on the computer readable storage medium to:

identify one or more contiguous gate array fill circuits in the initial integrated circuit design having a contiguous circuit area corresponding to a circuit area requirement of the gate array logic element; and

replace the identified contiguous gate array fill circuits with the gate array logic element in the integrated circuit design.

10. The computer program product of claim 7, further comprising computer program instructions stored on the computer readable storage medium to:

position a plurality of logic cells aligned on the single step size grid in the integrated circuit design; and

position one or more gate array fill circuits in the space between the adjacent logic cells and aligned with the single step size grid beginning with a single step size grid location immediately adjacent to at least one of the adjacent logic cells to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits and thereby to define the least common multiple step size grid between the adjacent logic cells.

11. The computer program product of claim 7, wherein the instructions to determine an initial placement position of the fully configured gate array logic element comprises computer program instructions stored on the computer readable storage medium to:

make available for the initial placement position any position between adjacent logic cells in alignment with the single step size grid in which one or more gate array fill circuits are positioned in the initial integrated circuit design.

12. The computer program product of claim 7, wherein the at least one circuit design consideration includes circuit timing considerations.

13. An apparatus for positioning gate array circuits in an integrated circuit design, comprising

a processor unit

configured to:

receive an initial integrated circuit design including logic cells positioned aligned on a single step size grid and gate array fill circuits positioned in a space between adjacent logic cells, wherein the size of each gate array fill circuit is a multiple of a least common multiple step size, and wherein each gate array fill circuit is aligned with a least common multiple step size grid positioned between adjacent logic cells with respect to at least one of the adjacent logic cells and aligned with the single step size grid such that each least common multiple step size grid includes the maximum number of least common multiple step size grid cells that may be positioned in the space between the adjacent logic cells;

receive a gate array logic element design to be placed in the integrated circuit design;

automatically determine an initial placement position for the gate array logic element at any position between adjacent logic cells in alignment with the single step size grid based on at least one circuit design consideration;

after automatically determine the initial placement position for the gate array logic element;

when the initial placement position is not aligned with the least common multiple step size grid, automatically positioning the gate array logic element in a final position aligned with the least common multiple step size grid, wherein the final position is different from the initial position by a multiple of single step size grid cells; and

position automatically gate array fill circuits aligned with the least common multiple step size grid between adjacent logic cells to fill the space between adjacent logic cells unoccupied by the gate array logic element.

14. The apparatus of claim 13, wherein the processor unit is configured to:

automatically fill the space between adjacent logic cells in the initial integrated circuit design with one or more gate array fill circuits aligned with the least common multiple step size grid to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits.

15. The apparatus of claim 14, wherein the processor unit is configured to:

identify one or more contiguous gate array fill circuits in the initial integrated circuit design having a contiguous circuit area corresponding to a circuit area requirement of the gate array logic element; and

replace the identified contiguous gate array fill circuits with the gate array logic element in the integrated circuit design.

16. The apparatus of claim 13, wherein the processor unit is configured to provide the initial integrated circuit design by:

positioning a plurality of logic cells aligned on the single step size grid in the integrated circuit design; and

positioning one or more gate array fill circuits in the space between the adjacent logic cells and aligned with the single step size grid beginning with a single step size grid location immediately adjacent to at least one of the adjacent logic cells to fill the maximum amount of space between adjacent logic cells that is available for gate array fill circuits and thereby to define the least common multiple step size grid between the adjacent logic cells.

17. The apparatus of claim 13, wherein the processor unit is configured to:

make available for the initial placement position any position between adjacent logic cells in alignment with the single step size grid in which one or more gate array fill circuits are positioned in the initial integrated circuit design.