Integrated data model based framework for driving design convergence from architecture optimization to physical design closure

• US 8,276,107 B2
• Filed: 10/18/2010
• Issued: 09/25/2012
• Est. Priority Date: 10/18/2010
• Status: Expired due to Fees

• Current Assignee: Algotochip Corp.
• Original Assignee: Algotochip Corp.
• Inventors: Durbha, Ananth, Padmanabhan, Satish, Ng, Pius
• Primary Examiner(s): Garbowski, Leigh
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US12/906,785
• Publication Number:
  US 20120096417A1
• Time in Patent Office: 708 Days
• Field of Search: None
• US Class Current: 716/104
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.

Claims

1. A method to automatically synthesize a custom integrated circuit, comprising:

receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;

encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code;

receiving a look-ahead cost function during architecture optimization consistent with cost observed later in a design flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model;

automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model;

synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication; and

applying pre and post fix tags to indicate if the grouping of cells in a hierarchy is a hard or soft constraint.

2. The method of claim 1, further comprising creating a sideband communication channel and protocol that enables inter-tool and intra-flow communications.

3. The method of claim 1, further comprising storing names with certain pre/post fix to indicate a critical path from the architecture level knowledge.

4. The method of claim 1, further comprising indicating placement constraints for optimal timing with one of:

macro blocks name, hierarchy name, pragma, comment, dummy module, wrapper module.

5. The method of claim 1, further comprising performing look ahead to detect true critical paths as part of cost function evaluation during optimization candidate search.

6. The method of claim 1, wherein the one or more constraints comprises one of:

register transfer language (RTL) constraint, floor plan constraint, physical constraint, timing constraint, power constraint, system level constraint.

7. The method of claim 1, further comprising providing constraint information to the data model through a netlist naming protocol.

8. The method of claim 1, further comprising performing static profiling or dynamic profiling of the computer readable code.

9. The method of claim 8, further comprising converting static profiling or dynamic profiling of the computer readable code into resource constraints for cost modeling as well as physical design optimization.

10. The method of claim 1, further comprising automatically generating firmware or software development kit (SDK) for the custom integrated circuit to run the computer readable code.

11. The method of claim 1, further comprising selecting an architecture based on the computer readable code.

12. The method of claim 11, further comprising linking the assembly code to generate firmware for the selected architecture.

13. The method of claim 12, further comprising optimizing the architecture based on profiled firmware.

14. The method of claim 10, further comprising performing cycle accurate simulation of the firmware.

15. The method of claim 10, further comprising performing dynamic profiling of the firmware.

16. The method of claim 11, further comprising optimizing the architecture based on the assembly code.

17. The method of claim 1, further comprising optimizing the architecture based on static and dynamic profiling of the computer readable code.

18. The method of claim 1, further comprising compiling the computer readable code into assembly code.

19. The method of claim 11, comprising further generating register transfer level (RTL) code for the selected architecture and synthesizing the RTL code.