Profiling of software and circuit designs utilizing data operation analyses

• US 8,276,135 B2
• Filed: 11/07/2002
• Issued: 09/25/2012
• Est. Priority Date: 11/07/2002
• Status: Expired due to Fees

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L.
• Primary Examiner(s): VU, TUAN A
• Application Number:
  US10/289,640
• Publication Number:
  US 20040093589A1
• Time in Patent Office: 3,610 Days
• Field of Search: 710/8, 709/217, 717/158, 717/130, 717/114, 717/149, 717159-163, 701/1, 713/1, 713/324, 713/100, 713/375, 703/14, 703/20, 703/26, 703/4, 716/1, 716/18, 712/17, 714/25
• US Class Current: 717/161
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The present invention is a method, system, software and data structure for profiling programs, other code, and adaptive computing integrated circuit architectures, using a plurality of data parameters such as data type, input and output data size, data source and destination locations, data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, memory usage, and data persistence. The profiler of the invention accepts a data set as input, and profiles a plurality of functions by measuring a plurality of data parameters for each function, during operation of the plurality of functions with the input data set, to form a plurality of measured data parameters. From the plurality of measured data parameters, the profiler generates a plurality of data parameter comparative results corresponding to the plurality of functions and the input data set. Based upon the measured data parameters, portions of the profiled code are selected for embodiment as computational elements in an adaptive computing IC architecture.

Claims

1. A computer-implemented method for generating a reconfigurable architecture for a hardware adaptive computing engine (ACE) having a set of one or more matrices, each matrix comprising a set of one or more computation units, each computation unit comprising a set of one or more computational elements, and the reconfigurable architecture being reconfigurable in real time when ACE configuration code is executed, the method comprising:

profiling ACE configuration code to make measurements of a plurality of data parameters, wherein the code is executable and embodies a plurality of algorithmic elements, and wherein the code, when executed, causes a first function to be performed and a second function to be performed;

based on the plurality of data parameters measured, selecting which of the algorithmic elements of the code are to be implemented in the reconfigurable architecture for the first function and the second function;

receiving a plurality of hardware architecture descriptions of the sets of matrices, computation units and computational elements;

based on the hardware architecture descriptions and the selected algorithmic elements, selecting one or more computational elements;

selecting an interconnection network for causing the selected one or more computational elements to be connected together in a first architecture configuration in real time for performing the first function, and

switching, when the ACE configuration code is executing, the interconnection network for causing the selected one or more computational elements to be connected together in a second architecture configuration for performing the second function, the switching including changing the connections among the computational elements based on the profiling to cause the computational elements to be connected in a first architecture configuration for performing the first function and cause the computational elements to be connected in a second, different architecture configuration for performing the second function.

2. The method of claim 1, further comprising:

profiling of the reconfigurable architecture to obtain performance results; and

iteratively performing the selecting one or more computational elements, the switching the interconnection network, and the profiling until the results are optimal.

3. The method of claim 2, wherein the optimal results are determined based on comparing the data parameters measured from profiling each generation of the reconfigurable architecture for the hardware adaptive computing engine.

4. The method of claim 2, wherein the optimal results are determined based on comparing the data parameters measured from profiling the reconfigurable architecture for the hardware adaptive computing engine to a predetermined criterion.

5. The method of claim 1, wherein the code comprises a first program to perform the first function and a second, different program to perform the second function.

6. The method of claim 1, wherein the code comprises one program having a first code portion to perform the first function and a second code portion to perform the second function.

7. The method of claim 1, wherein the reconfigurable architecture for the hardware adaptive computing engine is embodied in a single integrated circuit.

8. The method of claim 1, wherein the selecting an interconnection network further comprises:

determining a hardware location in the hardware adaptive computing engine for respective ones of the selected one or more computational elements.

9. The method of claim 1, further comprising:

based on the plurality of data parameters measured, determining power consumption for each algorithmic element of the plurality of algorithmic elements.

10. The method of claim 1, further comprising providing reconfiguration information to connect the selected one or more computational elements together in the first and second configurations.

11. A computer-implemented method for modifying the configuration of a reconfigurable architecture of a hardware adaptive computing engine (ACE) in real time when ACE configuration code is executed, the adaptive computing engine having a set of one or more matrices, each matrix comprising a set of one or more computation units, each computation unit comprising a set of one or more computational elements, the method comprising:

profiling ACE configuration code to determine a plurality of data parameters, wherein the code is executable and embodies a plurality of algorithmic elements, and wherein the code, when executed, causes a first function to be performed and a second function to be performed;

based on the plurality of data parameters measured, selecting which of the algorithmic elements of the code are to be implemented in the reconfigurable architecture for the first function and the second function;

reading a plurality of hardware architecture descriptions of the sets of matrices, computation units and computational elements;

based on the hardware architecture descriptions and the selected algorithmic elements, selecting one or more computational elements;

switching, when the ACE configuration code is executing, the interconnection network for causing the selected one or more computational elements to be connected together in a second architecture configuration for performing the second function, the switching including changing the connections among the computational elements based on the profiling to cause the computational elements to be connected in a first architecture configuration for performing the first function and cause the computational elements to be connected in a second, different architecture configuration for performing the second function.

12. The method of claim 11, wherein the modifying further comprises:

iteratively profiling the modified architecture configuration and changing the connections among the computational elements to obtain optimal performance results.

13. The method of claim 12, wherein the optimal results are determined based on comparing data parameters measured from profiling each of the configurations of the interconnections.

14. The method of claim 12, wherein the optimal results are determined based on comparing data parameters measured from profiling each modified architecture configuration.

15. The method of claim 11, wherein the code comprises a first program to perform a first function and a second, different program to perform a second function.

16. The method of claim 11, wherein the code comprises one program having a first code portion to perform a first function and a second code portion to perform a second function.

17. The method of claim 11, wherein the data parameters are a plurality of static and dynamic data parameters comprising at least one of the following data parameters:

locality of reference parameter;

data location for static data;

data type;

input data size;

output data size;

data source location;

data destination location;

data pipeline length;

distance of data movement;

speed of data movement;

data access frequency;

number of data load/stores;

cache usage;

register usage;

memory usage, and data persistence.

18. An integrated circuit having a reconfigurable architecture, the integrated circuit being reconfigurable in real time when configuration code is executed, the integrated circuit comprising:

a profiler for profiling configuration code to make measurements of a plurality of data parameters, wherein the code is executable to perform a first function of the code and a second function of the code and embodies a plurality of algorithmic elements

a plurality of computational elements;

control logic for;

a) selecting the algorithmic elements of the code that are to be implemented in the reconfigurable architecture for the first function and the second function based on the plurality of data parameters measured,

b) receiving a plurality of hardware architecture descriptions of the sets of matrices, computation units and computational elements, and

c) based on the hardware architecture descriptions and the selected algorithmic elements, selecting one or more computational elements; and

a reconfigurable interconnection network using real time execution of the configuration code for selectively connecting together the plurality of computational elements in a first configuration associated with the first function of the code, by switching, when the configuration code is executing, the interconnection network and causing the selected one or more computational elements to be connected together in a second architecture configuration in real time for performing the second function, the switching including changing connections among the plurality of computational elements based on the profiling to cause the plurality of computational elements to be connected in a second, different configuration for performing the second function of the code.

19. The integrated circuit of claim 18, wherein the control logic iteratively selects configurations based on the profiling to thereby achieve optimal results.

20. The integrated circuit of claim 19, wherein the control logic determines the optimal results based on comparing data parameters measured from profiling each of the configurations.

21. The integrated circuit of claim 19, wherein the control logic determines the optimal results based on comparing data parameters measured from profiling the configuration to a predetermined criterion.

22. The integrated circuit of claim 18, wherein the code comprises a first program to perform the first function and a second, different program to perform the second function.

23. The integrated circuit of claim 18, wherein the code comprises one program having a first code portion to perform the first function and a second code portion to perform the second function.

24. The integrated circuit of claim 18, further comprising providing reconfiguration information to selectively connect together the plurality of computational elements in the first and second configurations.