Bonding process for CMOS image sensor

• US 8,278,152 B2
• Filed: 11/25/2009
• Issued: 10/02/2012
• Est. Priority Date: 09/08/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Jen-Cheng, Yaung, Dun-Nian, Kuo, Chen-Cheng, Chen, Chen-Shien, Wuu, Shou-Gwo
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US12/626,296
• Publication Number:
  US 20100090304A1
• Time in Patent Office: 1,042 Days
• Field of Search: None
• US Class Current: 438/118
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

Claims

1. A method of making an integrated circuit (IC), comprising:

forming an electric device on a front side of a substrate;

forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device;

forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer;

forming an opening in the passivation layer, exposing the top metal pad;

forming a deep trench in the substrate through the opening without the deep trench extending through the top metal pad;

filling a conductive material in the deep trench and the opening, resulting in a through-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature;

removing excessive conductive material, forming a substantially planar surface;

forming a dielectric layer on the front side of the substrate after removing the excessive conductive material;

grinding the substrate from a backside to expose the TWV feature; and

etching the substrate in a scribe region from the backside to form a scribe-line trench.

2. The method of claim 1, further comprising:

forming a dielectric material layer on surfaces of the scribe-line trench; and

forming a coating solder mask (CSM) on the dielectric material layer.

3. The method of claim 2, further comprising:

forming an external lead on the backside of the substrate and on the CSM, the external lead being connected to the TWV feature; and

forming a solder bump on the CSM.

4. The method of claim 1, wherein the filling of the conductive material comprises:

forming an isolation layer in the opening and the deep trench;

performing a dry etch to the isolation layer to remove isolation layer on a first bottom surface of the opening and a second bottom surface of the deep trench;

forming a copper seed layer on the isolation layer, the first bottom surface and the second bottom surface, using physical vapor deposition (PVD); and

forming bulk copper on the copper seed layer by plating.

5. The method of claim 1, wherein the forming of the electric device comprises forming a complementary metal-oxide-semiconductor (CMOS) image sensing element on the front side of the substrate.

6. The method of claim 5, further comprising forming a plurality of color filters and a plurality of lens on the front side of the substrate.

7. The method of claim 1, further comprising forming an epoxy feature on the front side of the substrate within the scribe region.

8. The method of claim 1, further comprising attaching the substrate from the front side to a carrier wafer.

9. The method of claim 1, further comprising dicing the integrated circuit within the scribe-line trench.

10. A method of forming an integrated circuit, comprising:

forming a semiconductor device in a front surface of a silicon substrate;

forming a multilayer interconnection (MLI) on the semiconductor device from the front side of the silicon substrate;

forming a metal pad on the MIA, the metal pad being coupled with the semiconductor device;

forming a dielectric layer on the metal pad and the silicon substrate, the metal pad being embedded in the dielectric layer;

etching the dielectric layer to form a trench in the dielectric layer, exposing the metal pad and a portion of the dielectric layer adjacent to the metal pad within the trench;

performing a dielectric etch on the portion of the dielectric layer adjacent to the metal pad within the trench to form a via in the MLI;

performing a silicon etch to continue the via through the silicon substrate to form a through-silicon via (TSV);

performing copper metallization on the TSV and the trench; and

thereafter applying a chemical mechanical polishing (CMP) process.

11. The method of claim 10, wherein the performing of the copper metallization comprises:

forming a copper seed layer by sputtering; and

forming bulk copper on the copper seed layer by plating.

12. The method of claim 11, wherein the performing of the copper metallization further comprises, prior to the forming of the copper seed layer and the forming of the bulk copper:

forming an isolation layer in the trench and the TSV; and

performing a dry etch to the isolation layer to remove isolation layer on a first bottom surface of the trench and a second bottom surface of the TSV.

13. The method of claim 10, further comprising:

forming a passivation layer after the CMP process;

forming color filters on the passivation layer;

grinding the silicon substrate from a backside; and

providing a bonding mechanism on a backside of the integrated circuit, the bonding mechanism being connected to the TSV.

14. The method of claim 13, wherein the providing of the bonding mechanism comprises:

forming a coating solder mask (CSM) on the backside of the substrate;

forming a conductive feature extending from the CSM to the TSV; and

forming a solder ball on the conductive feature interposed between the solder ball and the CSM.

15. The method of claim 10, further comprising attaching the silicon substrate from the front surface to a carrier substrate.

16. An integrated circuit, comprising:

an electric device formed on a front side of a substrate;

a passivation layer formed on the front side of the substrate;

a metal pad embedded in the passivation layer and coupled with the electric device;

a through-wafer via (TWV) feature disposed in the substrate and extended to a backside of the substrate without passing through the metal pad, wherein the TWV feature is exposed on the backside of the substrate;

a pad-TWV metal feature embedded in the passivation layer and contacting the metal pad and the TWV feature, wherein an excess portion of the pad-TWV is removed such that the pad-TWV and the passivation layer have coplanar top surfaces;

a dielectric layer formed on the front side of the substrate after removal of the excess portion of the pad-TWV metal feature; and

a scribe-line trench etched in a scribe region of the backside of the substrate.

17. The integrated circuit of claim 16, further comprising a solder ball on the backside of the substrate in electrical connection with the TWV feature and a carrier substrate attached to the substrate from the front side.

18. The integrated circuit of claim 16, wherein the electric device comprises an imaging element selected from the group consisting of complementary metal-oxide-semiconductor (CMOS) image sensor, photodiode, and pinned photodiode;

and the integrated circuit further includes micro lens and color filters positioned on the front side of the substrate and aligned with the imaging element.

19. The integrated circuit of claim 16, wherein the TWV feature includes copper and is formed by a damascene process such that the TWV feature is formed proximate to the metal pad without the metal pad surrounding the TWV feature.