Metal-semiconductor intermixed regions

• US 8,278,200 B2
• Filed: 01/24/2011
• Issued: 10/02/2012
• Est. Priority Date: 01/24/2011
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Lavoie, Christian, Ning, Tak H., Ozcan, Ahmet S., Yang, Bin, Zhang, Zhen
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US13/012,043
• Publication Number:
  US 20120190192A1
• Time in Patent Office: 617 Days
• Field of Search: 438/584, 438/597, 438/660, 438/663, 438/664, 257/E21.091, 427/69, 427/78, 427/96.8, 427/497, 427/509
• US Class Current: 438/584
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence

Abstract

In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Claims

1. A non-transitory computer-readable medium storing a program of instructions executable by a machine for performing operations, said operations comprising:

depositing a first layer comprised of a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure;

removing a portion of the deposited first layer to expose the first intermix region;

depositing a second layer comprised of a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region;

removing a portion of the deposited second layer to expose the second intermix region; and

performing at least one anneal on the semiconductor structure, where no anneal is performed prior to removal of the portion of the deposited second layer where the removed portion of the deposited first layer comprises non-intermixed first metal, and where the removed portion of the deposited second layer comprises non-intermixed second metal.

2. The computer-readable medium of claim 1, where the first metal is the same as the second metal.

3. The computer-readable medium of claim 1, where the first metal comprises at least one of Co, Ti, Pt, Ni, Er, Yb and W.

4. The computer-readable medium of claim 1, where the first metal is the same as the second metal and where the first metal comprises at least one of Co, Ti, Pt, Ni, Er, Yb and W.

5. The computer-readable medium of claim 1, where the first metal is different from the second metal.

6. The computer-readable medium of claim 1, where depositing the first layer comprises sputtering the first layer onto the surface of the semiconductor structure.

7. The computer-readable medium of claim 1, where depositing the second layer comprises sputtering the second layer onto the first intermix region.

8. The computer-readable medium of claim 1, the operations further comprising:

depositing a third layer comprised of a third metal on the second intermix region, where depositing the third layer creates a third intermix region at an interface of the third layer and the second intermix region.

9. The computer-readable medium of claim 1, where performing the at least one anneal on the semiconductor structure consists of performing only one anneal on the semiconductor structure.

10. A method comprising:

depositing a first layer comprised of a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure;

removing a portion of the deposited first layer to expose the first intermix region;

depositing a second layer comprised of a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region;

removing a portion of the deposited second layer to expose the second intermix region; and

performing at least one anneal on the semiconductor structure, where no anneal is performed prior to removal of the portion of the deposited second layer where the removed portion of the deposited first layer comprises non-intermixed first metal, and where the removed portion of the deposited second layer comprises non-intermixed second metal.

11. The method of claim 10, where performing the at least one anneal comprises performing one anneal after removing the portion of the deposited second layer to expose the second intermix region.

12. The method of claim 10, where at least one of depositing the first layer and depositing the second layer comprises controlling an energy of incident atoms in order to achieve a desired characteristic of at least one of the first intermix region and the second intermix region.

13. The method of claim 12, where controlling the energy of the incident atoms comprises controlling an electric field in the trajectory of the incident atoms.

14. The method of claim 10, where at least one of depositing the first layer and depositing the second layer comprises performing ionized physical vapor deposition.

15. The method of claim 10, where at least one of depositing the first layer and depositing the second layer comprises controlling an energy of incident atoms in order to achieve a desired characteristic of at least one of the first intermix region and the second intermix region, where at least one of depositing the first layer and depositing the second layer comprises performing ionized physical vapor deposition, where controlling the energy of the incident atoms comprises controlling an electric field in the trajectory of the incident atoms.