Semiconductor device having a buried gate and method for manufacturing the same

• US 8,278,201 B2
• Filed: 07/30/2010
• Issued: 10/02/2012
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jang, Kyoung Chul
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US12/848,045
• Publication Number:
  US 20110180868A1
• Time in Patent Office: 795 Days
• Field of Search: None
• US Class Current: 438/589
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

According to the present invention, a method of manufacturing a semiconductor device includes forming a recess on a semiconductor substrate, forming a first gate electrode material and a hard mask layer on an entire surface including the recess, etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess, forming a second gate electrode material on an entire surface including the recess, and etching the second gate electrode material and separating the second gate electrode material.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a recess in a semiconductor substrate;

forming a first gate electrode pattern in a lower portion of the recess, the first gate electrode being a liner pattern over a bottom and a sidewall surface of the lower portion of the recess;

forming a second gate electrode pattern filling an upper portion of the recess and extending into the lower portion of the recess, the second gate electrode pattern being disposed over the first gate electrode pattern,

wherein the second gate electrode pattern has a larger width in the upper portion of the recess than in the lower portion of the recess.

2. The method of claim 1, the method further comprising:

forming a sacrificial layer over the substrate prior to forming the first gate electrode pattern, the sacrificial layer including one selected from the group consisting of a polysilicon layer, an oxide layer, a photo resist film, a carbon layer, and a combination thereof.

3. The method of claim 1, wherein the first gate electrode pattern includes a laminated structure of any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof, and

wherein the second gate electrode pattern includes tungsten W.

4. The method of claim 1, wherein the second gate electrode pattern is formed by filling the recess with a second gate electrode material and etching the second gate electrode material using an etch back process.

5. The method of claim 1, wherein the second gate electrode pattern has a conductivity that is higher than that of the first gate electrode pattern.

6. The method of claim 1, wherein the first and the second gate electrode patterns form an integrated buried gate.

7. A method of manufacturing a semiconductor device, comprising:

forming a recess in a semiconductor substrate;

forming a first gate electrode material over an entire surface of the semiconductor substrate including the recess;

etching the first gate electrode material to form a first gate electrode pattern in a lower portion of the recess;

forming a second gate electrode material over the semiconductor substrate and the first gate electrode pattern in the lower portion of the recess; and

etching the second gate electrode material to form a second gate electrode pattern,

wherein the second gate electrode pattern has a larger width in an upper portion of the recess than in a lower portion of the recess, and

wherein the first gate electrode pattern includes any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof.

8. A method of manufacturing a semiconductor device, comprising:

forming a recess in a semiconductor substrate, the recess having an upper portion and a lower portion;

forming a first gate electrode material over the recess;

etching the first gate electrode material to form a first gate electrode pattern over the lower portion of the recess, the first gate electrode pattern coating the lower portion of the recess;

forming a second gate electrode material in the upper and lower portions of the recess; and

etching the second gate electrode material to form a second gate electrode pattern extending at least partly into the lower portion of the recess, so that a portion of the second gate electrode pattern is coated with the first gate electrode pattern.

9. The method of claim 8, wherein the first gate electrode pattern is formed of any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al, and a combination thereof, and

wherein the second gate electrode pattern includes tungsten W.

10. The method of claim 8, wherein the second gate electrode pattern is formed by an etch back process.