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Structure and method for forming planar gate field effect transistor with low resistance channel region

  • US 8,278,686 B2
  • Filed: 05/09/2011
  • Issued: 10/02/2012
  • Est. Priority Date: 12/13/2007
  • Status: Active Grant
First Claim
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1. A vertically-conducting planar-gate field effect transistor comprising:

  • a silicon region of a first conductivity type;

    a silicon-germanium layer extending over the silicon region;

    gate electrode laterally extending over but being insulated from the silicon-germanium layer;

    a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region; and

    source region of the first conductivity type extending in the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

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