Structure and method for forming planar gate field effect transistor with low resistance channel region

• US 8,278,686 B2
• Filed: 05/09/2011
• Issued: 10/02/2012
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James, Wang, Qi
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/103,728
• Publication Number:
  US 20110215377A1
• Time in Patent Office: 512 Days
• Field of Search: 257/192, 257/335, 257/343, 257/345, 257/368, 257/616, 257/E29.066, 257/E29.297, 257/E29.298, 257/E21.182, 438/197, 438/230, 438/933
• US Class Current: 257/192
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Claims

1. A vertically-conducting planar-gate field effect transistor comprising:

a silicon region of a first conductivity type;

a silicon-germanium layer extending over the silicon region;

gate electrode laterally extending over but being insulated from the silicon-germanium layer;

a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region; and

source region of the first conductivity type extending in the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

2. The transistor of claim 1 wherein the portion of the silicon-germanium layer through which the source region extends is of first conductivity type, and the portion of the silicon-germanium layer through which the body region extends is of the second conductivity type.

3. A method of forming a vertically-conducting planar-gate field effect transistor comprising:

forming a silicon-germanium layer over a silicon region of a first conductivity type;

forming a gate electrode laterally extending over but insulated from the silicon-germanium layer;

forming a body region of a second conductivity type extending in the silicon-germanium layer and the silicon region; and

forming a source region of the first conductivity type extending at least into the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

4. The method of claim 3 further comprising:

prior to forming source regions, forming dielectric spacers along sidewalls of the gate electrode.