Structure and method for forming laterally extending dielectric layer in a trench-gate FET

• US 8,278,704 B2
• Filed: 10/19/2010
• Issued: 10/02/2012
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Andrews, John Tracey
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): MCCALL SHEPARD, SONYA D
• Application Number:
  US12/907,805
• Publication Number:
  US 20110031551A1
• Time in Patent Office: 714 Days
• Field of Search: 257/330, 257/333, 257/E21.12, 257/E29.242, 257/E29.262, 438/259, 438/270, 438/271
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A FET is formed as follows. A trench is formed in a silicon region. A shield electrode is formed in a bottom portion of the trench. The shield electrode is insulated from adjacent silicon region by a shield dielectric. A silicon nitride layer is formed over a surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode and shield dielectric. A layer of LTO is formed over the silicon nitride layer such that those portions of the LTO layer extending over the surface of the silicon region adjacent the trench are thicker than the portion of the LTO layer extending over the shield electrode. The LTO layer is uniformly etched back such that a portion of the silicon nitride layer becomes exposed while portions of the silicon nitride layer remain covered.

Claims

1. A method of forming a FET, comprising:

forming a trench in a silicon region;

forming a shield electrode in a bottom portion of the trench, the shield electrode being insulated from adjacent silicon region by a shield dielectric;

forming a nitride etch resistant layer extending over a surface of the silicon region adjacent the trench, along trench sidewalls, and over the shield electrode and the shield dielectric;

forming a silicon nitride layer extending over the nitride etch resistant layer along the surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode and the shield dielectric;

forming a layer of low temperature oxide (LTO) over the silicon nitride layer such that those portions of the LTO layer extending over the surface of the silicon region adjacent the trench are thicker than the portion of the LTO layer extending over the shield electrode; and

uniformly etching back the LTO layer such that a portion of the silicon nitride layer extending over the shield electrode and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the LTO layer.

2. The method of claim 1 further comprising:

removing the exposed portion of the silicon nitride layer over the shield electrode using an anisotropic etch process; and

forming a dielectric layer extending over the shield electrode using a local oxidation of silicon (LOCOS) process.

3. The method of claim 1 wherein the nitride etch resistant layer comprises pad oxide, and extends over the surface of the silicon region adjacent to the trench and along the trench sidewalls and bottom, wherein the step of removing the exposed portion of the silicon nitride layer exposes a portion of the pad oxide layer extending along the trench bottom.

4. The method of claim 1 wherein the silicon nitride layer is formed using a low pressure chemical vapor deposition (LPCVD) process.

5. The method of claim 2 further comprising:

prior to forming the dielectric layer, removing the remaining portions of the LTO layer.

6. The method of claim 5 further comprising:

removing remaining portions of the nitride layer;

forming a gate oxide along upper trench sidewalls; and

forming a recessed gate electrode over the shield electrode in the trench.

7. A method of forming a FET, comprising:

forming a trench in a silicon region;

forming a shield electrode in a bottom portion of the trench, the shield electrode being insulated from adjacent silicon region by a shield dielectric;

forming an insulating layer extending over a surface of the silicon region adjacent the trench, along trench sidewalls, and over the shield electrode;

forming an oxidation barrier layer extending over the insulating layer along the surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode;

forming a protective layer over the oxidation barrier layer inside and outside the trench;

partially removing the protective layer such that a portion of the oxidation barrier layer extending at least over the shield electrode becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer;

removing the exposed portion of the oxidation barrier layer from over the shield electrode, wherein removing the exposed portion of the oxidation barrier layer exposes a portion of the insulating layer extending over the shield electrode; and

forming a dielectric layer over the shield electrode.

8. The method of claim 7 wherein the oxidation barrier layer comprises silicon nitride, and the step of removing the exposed portion of the oxidation barrier layer is carried out using an anisotropic etch process.

9. The method of claim 7 wherein the dielectric layer is formed using a local oxidation of silicon (LOCOS) process.

10. The method of claim 7 further comprising:

prior to forming the dielectric layer, removing the remaining portions of the protective layer.

11. The method of claim 7 further comprising:

removing remaining portions of the oxidation barrier layer;

forming a gate oxide along upper trench sidewalls; and

forming a recessed gate electrode over the dielectric layer in the trench.

12. The method of claim 7 wherein the protective layer comprises low temperature oxide (LTO).

13. The method of claim 7 wherein the portion of the protective layer extending along the surface of the silicon region adjacent the trench is thicker than the portion of the protective layer extending over the shield electrode.

14. The method of claim 8 wherein the silicon nitride layer is formed using a low pressure chemical vapor deposition (LPCVD) process.

15. The method of claim 13 wherein the step of partially removing the protective layer comprises:

uniformly etching the protective layer.

16. An intermediary of a FET, comprising:

a trench extending into a silicon region;

a shield electrode recessed in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric;

an oxidation barrier layer extending over a surface of the silicon region adjacent the trench and along the trench sidewalls but being discontinuous over the shield electrode;

an insulating layer extending over the surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode, the insulating layer being covered by the oxidation barrier layer except for the portion of the insulating layer extending over the shield electrode; and

a protective layer extending over all horizontally extending portions of the oxidation barrier layer.

17. The structure of claim 16 wherein the oxidation barrier layer has a substantially uniform thickness and comprises silicon nitride.

18. The structure of claim 16 wherein the protective layer comprises low temperature oxide (LTO).

19. The structure of claim 16 wherein the insulating layer has a substantially uniform thickness and comprises oxide.

20. The structure of claim 16 wherein the protective layer has a substantially non-uniform thickness, a thickness of the protective layer near a surface of the silicon region being greater than a thickness of the protective layer near the shield electrode.

21. The structure of claim 16 further comprising a dielectric layer extending over the shield electrode.

22. An intermediary of a FET, comprising:

a trench extending into a silicon region;

an oxidation barrier layer extending over a surface of the silicon region adjacent the trench and along the trench sidewalls but being discontinuous along the trench bottom;

an insulating layer extending over the surface of the silicon region adjacent the trench and along the trench sidewalls and bottom, the insulating layer being covered by the oxidation barrier layer except for the portion of the insulating layer extending along the trench bottom; and

a protective layer extending over all horizontally extending portions of the oxidation barrier layer.

23. The structure of claim 22 wherein the insulating layer has a substantially uniform thickness and comprises oxide.

24. The structure of claim 22 wherein the oxidation barrier layer has a substantially uniform thickness and comprises silicon nitride.

25. The structure of claim 22 wherein the protective layer comprises low temperature oxide (LTO).

26. The structure of claim 22 wherein the protective layer has a substantially non-uniform thickness, a thickness of the protective layer near a surface of the silicon region being greater than a thickness of the protective layer near the trench bottom.

27. The structure of claim 22 further comprising a dielectric layer extending along the trench bottom.