Field effect transistor with gated and non-gated trenches

• US 8,278,705 B2
• Filed: 06/02/2011
• Issued: 10/02/2012
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kraft, Nathan
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/152,041
• Publication Number:
  US 20110303975A1
• Time in Patent Office: 488 Days
• Field of Search: 257/330, 257/331, 257/332, 257/333, 257/E29.257, 438/257, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Claims

1. A FET comprising:

a plurality of trenches extending into a semiconductor region of a first conductivity type, the plurality of trenches comprising a plurality of gated trenches and a plurality of non-gated trenches;

a body region of a second conductivity in the semiconductor region between adjacent trenches;

a dielectric material filling a bottom portion of each of the gated and non-gated trenches;

a gate electrode in each gated trench; and

a conductive material of the second conductivity type in each non-gated trench such that the conductive material contacts corresponding body regions along sidewalls of the non-gated trench.

2. The FET of claim 1 further comprising:

a source region of the first conductivity type in each body region, wherein the conductive material in each non-gated trench contacts corresponding source regions along sidewalls of the non-gated trench; and

a source interconnect layer contacting each source region and each conductive material.

3. The FET of claim 1 wherein the dielectric material in each non-gated trench has a top surface above a bottom surface of the body region.

4. The FET of claim 2 wherein each source region extends across an entire width of a mesa region bounded along the lateral dimension by two adjacent trenches.

5. The FET of claim 1 wherein the semiconductor region comprises a highly doped substrate and an overlying epitaxial layer, and the body region is formed in an upper portion of the epitaxial layer.

6. The FET of claim 1 wherein the conductive material comprises polysilicon of the second conductivity type.

7. The FET of claim 1 wherein one non-gated trench is arranged between every two adjacent gated trench.

8. The FET of claim 1 wherein two or more non-gated trenches are formed between every two adjacent gated trenches.