Method of manufacturing photomask and method of repairing optical proximity correction

• US 8,278,762 B2
• Filed: 09/28/2009
• Issued: 10/02/2012
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Ling-Chieh, Lee, Chien-Fu, Huang, I-Hsiung
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/568,027
• Publication Number:
  US 20100013105A1
• Time in Patent Office: 1,100 Days
• Field of Search: 257/774, 257/773, 257/734, 257/E23.01, 716/19
• US Class Current: 257/774
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.

Claims

1. An integrated circuit, comprising:

a plurality of patterned layers and a plurality of contact plugs, wherein at least one contact plug among the plurality of contact plugs has an elliptic shape in a top view, wherein the at least one contact plug having an elliptic shape in a top view is one or both of a pair of neighboring contact plugs.

2. The integrated circuit of claim 1, wherein both of the pair of contact plugs have an elliptic shape, and major axes of the elliptic shapes of the pair of contact plugs are oriented in the same direction.

3. The integrated circuit of claim 1, wherein the plurality of patterned layers includes an upper patterned layer and a lower patterned layer that are respectively over and under the pair of contact plugs and both relate to the pair of contact plugs.

4. The integrated circuit of claim 3, wherein the upper patterned layer and the lower patterned layer each comprises a plurality of conductive lines.

5. The integrated circuit of claim 4, wherein the at least one contact plug is connected with a first conductive line in the upper patterned layer and with a second conductive line in the lower patterned layer, and a major axis of the elliptic shape of the at least one contact plug is parallel or perpendicularly to the first conductive line or the second conductive line.

6. The integrated circuit of claim 1, wherein the plurality of patterned layers includes an upper patterned layer and a lower patterned layer that are respectively over and under the at least one contact plug and both relate to the at least one contact plug.

7. The integrated circuit of claim 6, wherein the upper patterned layer and the lower patterned layer each comprises a plurality of conductive lines.

8. The integrated circuit of claim 7, wherein the at least one contact plug is connected with a first conductive line in the upper patterned layer and with a second conductive line in the lower patterned layer, and a major axis of the elliptic shape of the at least one contact plug is parallel or perpendicularly to the first conductive line or the second conductive line.

9. The integrated circuit of claim 6, wherein the at least one contact plug is located in a dielectric layer as a first patterned layer among the plurality of patterned layers, and the plurality of patterned layers also includes a second patterned layer at the same level of the at least one contact plug.

10. The integrated circuit of claim 9, wherein

the lower patterned layer includes a plurality of active areas,

the upper patterned layer includes a plurality of interconnect lines, and

the second patterned layer includes a plurality of gates.

11. An integrated circuit, comprising a plurality of patterned layers and a plurality of contact plugs, wherein at least one contact plug among the plurality of contact plugs has a center shift relative to at least one of

a part of an upper patterned layer over and relating to the at least one contact plug, and

a part of a lower patterned layer under and relating to the at least one contact plug, wherein

the part of the upper patterned layer and the part of the lower patterned layer each correspond to the at least one contact plug in position,

the at least one contact plug is located in a dielectric layer as a first patterned layer among the plurality of patterned layers,

the plurality of patterned layers also includes a second patterned layer at the same level of the at least one contact plug,

the lower patterned layer includes a plurality of active areas,

the upper patterned layer includes a plurality of interconnect lines, and

the second patterned layer includes a plurality of gates.

12. The integrated circuit of claim 11, wherein the upper patterned layer and the lower patterned layer each comprises a plurality of conductive lines.

13. An integrated circuit, comprising a plurality of patterned layers and a plurality of contact plugs, wherein at least one contact plug among the plurality of contact plugs has an elliptic shape and has a center shift relative to at least one of

a part of an upper patterned layer over and relating to the at least one contact plug, and

a part of a lower patterned layer under and relating to the at least one contact plug,

wherein the part of the upper patterned layer and the part of the lower patterned layer each correspond to the at least one contact plug in position.

14. The integrated circuit of claim 13, wherein the upper patterned layer and the lower patterned layer each comprises a plurality of conductive lines.

15. The integrated circuit of claim 14, wherein the at least one contact plug is connected with a first conductive line in the upper patterned layer and with a second conductive line in the lower patterned layer, and a major axis of the elliptic shape of the at least one contact plug is parallel or perpendicularly to the first conductive line or the second conductive line.

16. The integrated circuit of claim 13, wherein the at least one contact plug is located in a dielectric layer as a first patterned layer among the plurality of patterned layers, and the plurality of patterned layers also includes a second patterned layer at the same level of the at least one contact plug.

17. The integrated circuit of claim 16, wherein

the lower patterned layer includes a plurality of active areas,

the upper patterned layer includes a plurality of interconnect lines, and

the second patterned layer includes a plurality of gates.