System including an offset voltage adjusted to compensate for variations in a transistor

• US 8,278,893 B2
• Filed: 07/16/2008
• Issued: 10/02/2012
• Est. Priority Date: 07/16/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Motz, Mario
• Primary Examiner(s): Tran, Nguyen
• Application Number:
  US12/174,261
• Publication Number:
  US 20100013448A1
• Time in Patent Office: 1,539 Days
• Field of Search: 323/65, 323/68, 323/69, 323/74, 323/76, 323/223, 323/271, 323/272, 323/273, 323/311, 323/312, 323/314, 323/315, 327/530, 327/535, 327/538, 327/539, 327/540, 327/541
• US Class Current: 323/273
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A system including a first transistor, a first capacitor and a circuit. The first transistor has a first control input and is configured to regulate an output voltage. The first capacitor is coupled at one end to the first control input and at another end to a circuit reference. The circuit is configured to provide a first voltage to the first control input, where the first voltage includes an offset voltage that is referenced to the output voltage and adjusted to compensate for variations in the first transistor.

Claims

1. A system, comprising:

a first transistor having a first control input and configured to regulate an output voltage;

a first capacitor directly connected at one end to the first control input and directly connected at another end to a circuit reference; and

a circuit configured to provide a first voltage to the first control input, wherein the circuit comprises;

a first compensation circuit configured to provide an offset voltage that is part of the first voltage and referenced to the output voltage, wherein the first compensation circuit includes a compensation transistor that is similar to the first transistor such that variations in temperature and process changes affect both the compensation transistor and the first transistor and the compensation transistor is configured to vary the offset voltage to compensate for the variations in temperature and the process changes in the first transistor.

2. The system of claim 1, wherein the circuit comprises:

an operational transconductance amplifier configured to provide a control voltage, wherein the offset voltage is added to the control voltage to provide the first voltage.

3. The system of claim 1, comprising:

a second transistor having a second control input and coupled in series with the first transistor, wherein the first transistor and the second transistor are between a power supply voltage and the output voltage.

4. The system of claim 3, wherein the first transistor is a low voltage NMOS transistor configured to be a source follower and the second transistor is a high voltage NMOS transistor.

5. The system of claim 3, comprising:

a second capacitor directly connected at one end to the second control input and directly connected at another end to the circuit reference.

6. The system of claim 3, comprising:

a second compensation circuit configured to provide a second voltage to the second control input, wherein the second compensation circuit references the second voltage to the output voltage and varies the second voltage to compensate for variations in temperature and process changes in the second transistor.

7. A system, comprising:

a first transistor having a drain/source path and configured to regulate an output voltage at an output;

a capacitor directly connected to one side of the drain/source path of the first transistor and configured to provide current to the output through the first transistor; and

a device directly connected to the one side of the drain/source path of the first transistor and configured to dampen current from a power supply to provide dampened current and charge the capacitor with the dampened current, wherein the device is one of a resistor, a transconductance amplifier, and a current source including a current mirror pair of transistors.

8. The system of claim 7, wherein the first transistor is an NMOS transistor configured to be a source follower and having a drain coupled to one end of the capacitor.

9. The system of claim 7, wherein the device is the current source and the current source regulates current via voltage on the capacitor.

10. The system of claim 7, comprising:

a circuit configured to provide a voltage to a control input of the first transistor, wherein the circuit comprises;

a compensation circuit configured to provide an offset voltage and adjust the offset voltage to compensate for variations in the first transistor, wherein the offset voltage is added to another voltage to provide the voltage.

11. The system of claim 7, comprising an overload circuit configured to shunt current away from the capacitor.

12. The system of claim 7, comprising an underload circuit configured to shunt current around the device.

13. The system of claim 7, comprising:

a second transistor coupled in series with the first transistor between the power supply and the output.

14. A method for providing an output voltage comprising:

receiving a first voltage at a first control input of a first transistor;

regulating the output voltage via the first transistor;

compensating frequency responses via a capacitor directly connected at one end to the first control input and directly connected at another end to a circuit reference;

providing the first voltage to the first control input via a circuit that includes a compensation circuit;

providing an offset voltage that is part of the first voltage and referenced to the output voltage via the compensation circuit that include a compensation transistor that is similar to the first transistor such that variations in temperature and process changes affect both the compensation transistor and the first transistor; and

varying the offset voltage via the compensation transistor to compensate for the variations in temperature and the process changes in the first transistor.

15. The method of claim 14, wherein providing the first voltage comprises:

providing a control voltage via an operational transconductance amplifier; and

adding the offset voltage to the control voltage.

16. The method of claim 14, comprising:

receiving a second voltage at a second control input of a second transistor that is cascoded in series with the first transistor between a power supply voltage and the output voltage.

17. The method of claim 16, comprising:

providing the second voltage referenced to the output voltage; and

varying the second voltage to compensate for variations in temperature and process changes in the second transistor.

18. A method for providing an output voltage at an output comprising:

regulating the output voltage via a first transistor having a drain/source path;

dampening current from a power supply via a device, which is one of a resistor, a transconductance amplifier, and a current source including a current mirror pair of transistors, directly connected to one side of the drain/source path of the first transistor to provide dampened current;

charging a capacitor directly connected to the one side of the drain/source path of the first transistor with the dampened current; and

discharging the capacitor directly connected to the one side of the drain/source path of the first transistor through the first transistor to provide a current to the output.

19. The method of claim 18, comprising:

shunting at least part of the dampened current away from the capacitor.

20. The method of claim 18, comprising:

shunting at least part of the current from the power supply around the device and to the capacitor.

21. The method of claim 18, comprising:

providing a voltage to a control input of the first transistor, wherein providing the voltage comprises;

providing an offset voltage;

adjusting the offset voltage to compensate for variations in the first transistor; and

adding the offset voltage to another voltage to provide the voltage.

22. The method of claim 18, comprising:

providing a voltage to a control input of a second transistor coupled in series with the first transistor between the power supply and the output.