Divider circuit
First Claim
1. A divider circuit comprising:
- a shift register configured to output 2X pulse signals in accordance with a first clock signal and a second clock signal, wherein X is a natural number greater than or equal to 2; and
a divided signal output circuit configured to output a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals,wherein the divided signal output circuit comprises;
X first transistors each having a source, a drain, and a gate,wherein the shift register is configured to separately supply the respective gates of the X first transistors with the first to X-th pulse signals among the 2X pulse signals, andwherein the X first transistors are configured to control whether voltage of a signal to be the third clock signal is set to first voltage; and
X second transistors each having a source, a drain, and a gate,wherein the shift register is configured to separately supply the respective gates of the X second transistors with (X+1)-th to 2X-th pulse signals among the 2X pulse signals, andwherein the X second transistors are configured to control whether voltage of a signal to be the third clock signal is set to second voltage.
1 Assignment
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Accused Products
Abstract
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.
23 Citations
20 Claims
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1. A divider circuit comprising:
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a shift register configured to output 2X pulse signals in accordance with a first clock signal and a second clock signal, wherein X is a natural number greater than or equal to 2; and a divided signal output circuit configured to output a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals, wherein the divided signal output circuit comprises; X first transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X first transistors with the first to X-th pulse signals among the 2X pulse signals, and wherein the X first transistors are configured to control whether voltage of a signal to be the third clock signal is set to first voltage; and X second transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X second transistors with (X+1)-th to 2X-th pulse signals among the 2X pulse signals, and wherein the X second transistors are configured to control whether voltage of a signal to be the third clock signal is set to second voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A divider circuit comprising:
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a first unit divider circuit configured to generate a third clock signal in accordance with a first clock signal and a second clock signal, wherein a cycle of the third clock signal is X times longer than a cycle of the first clock signal, and wherein X is a natural number greater than or equal to 2; and a second unit divider circuit configured to generate a fourth clock signal in accordance with the third clock signal, wherein a cycle of the fourth clock signal is a cycle K times longer than the cycle of the third clock signal, and wherein K is a natural number greater than or equal to 2, wherein the first unit divider circuit comprises; a shift register configured to output 2X pulse signals in accordance with the first clock signal and the second clock signal; and a divided signal output circuit configured to output the third clock signal in accordance with the 2X pulse signals, wherein the divided signal output circuit comprises; X first transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X first transistors with the first to X-th pulse signals among the 2X pulse signals, and wherein the X first transistors are configured to control whether voltage of a signal to be the third clock signal is set to first voltage; and X second transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X second transistors with (X+1)-th to 2X-th pulse signals among the 2X pulse signals, and wherein the X second transistors are configured to control whether voltage of a signal to be the third clock signal is set to second voltage. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A divider circuit comprising:
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a shift register configured to output a plurality of pulse signals comprising a first pulse signal, a second pulse signal, a third pulse signal, and a fourth pulse signal in accordance with a first clock signal and a second clock signal; and a divided signal output circuit configured to output a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the plurality of pulse signals, wherein X is a natural number greater than or equal to 2, wherein the divided signal output circuit comprises; a plurality of first transistors configured to control whether voltage of a signal to be the third clock signal is set to first voltage, the plurality of first transistors comprising at least two transistors; and a plurality of second transistors configured to control whether voltage of a signal to be the third clock signal is set to second voltage, the plurality of second transistors comprising at least two transistors, wherein the shift register is configured to supply a gate of one of the two transistors comprised in the plurality of first transistors with one of the first pulse signal and the second pulse signal, wherein the shift register is configured to supply a gate of the other of the two transistors comprised in the plurality of first transistors with the other of the first pulse signal and the second pulse signal, wherein the shift register is configured to supply a gate of one of the two transistors comprised in the plurality of second transistors with one of the third pulse signal and the fourth pulse signal, and wherein the shift register is configured to supply a gate of the other of the two transistors comprised in the plurality of second transistors with the other of the third pulse signal and the fourth pulse signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification