Reference current generating circuit

• US 8,278,996 B2
• Filed: 03/03/2010
• Issued: 10/02/2012
• Est. Priority Date: 09/02/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miki, Kazuhiko, Takahashi, Toru
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US12/716,831
• Publication Number:
  US 20110050330A1
• Time in Patent Office: 944 Days
• Field of Search: 327/540, 327/541, 327/103
• US Class Current: 327/541
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A reference current generating circuit includes an operational amplifier having one input terminal to receive a reference voltage and a field effect transistor having a gate to receive an output voltage of the operational amplifier. k resistors (k is an integer not less than 2) are connected in series to a drain of the field effect transistor, and a voltage at one of connection points of the resistors is feed backed to the other input terminal of the operational amplifier. A switch selects one of the connection points of the resistors and applies the voltage of the selected connection point as a reference voltage to a gate of a reference transistor to generate a reference current.

Claims

1. A reference current generating circuit, comprising:

an operational amplifier having one input terminal to receive a reference voltage;

N first field effect transistors (N is integer) each having a gate to commonly receive an output voltage of the operational amplifier and a drain;

a series circuit including a plurality of resistors connected in series and having one terminal connected to each of drains of the first field effect transistors and feed backing a voltage at one of connection points of the resistors to the other input terminal of the operational amplifier;

M second field effect transistors (M is an integer not less than

     2) each having a gate to commonly receive an output voltage of the operational amplifier; and

a plurality of first switches to select the second field effect transistors to generate a reference current by merging current through each of the selected second field effect transistors;

a third field effect transistor having a gate to receive the reference current;

a sense amplifier to compare a drain current of the third field effect transistor with an input current;

an automatic trimming value decision circuit to decide a trimming value so as to set a difference between the drain current and the input current to be zero;

a non-volatile memory to store the trimming value determined by the automatic trimming value decision circuit;

a writing control circuit to control the writing in the non-volatile memory; and

a trimming control circuit to adjust a number of the second field effect transistors to be selected by the first switches based on either one of the trimming values decided by the automatic trimming value decision circuit or stored in the non-volatile memory.

2. The reference current generating circuit according to claim 1, wherein the reference current generating circuit includes a second switch to selectively connect one connection point of the plurality of resistors to the other terminal of the operational amplifier.

3. The reference current generating circuit according to claim 1, wherein the size and shape of the first field effect transistors are the same as those of the second field effect transistors.

4. The reference current generating circuit according to claim 3, wherein the respective second field effect transistors output same amount of drain current.

5. The reference current generating circuit according to claim 1, wherein the trimming value is written in the non-volatile memory before shipment in advance and the first switches are controlled by the trimming value read out from the non-volatile memory when power is on.

6. The reference current generating circuit according to claim 1, wherein a band gap reference voltage is used as the reference voltage.

7. The reference current generating circuit according to claim 1, further including a capacitor connected to the gate of the first field effect transistor.

8. The reference current generating circuit according to claim 1, wherein the first switches are set so that the reference current value is within an intermediate area between a lower limit of the on-cell current distribution and an upper limit of the off-cell current distribution.

9. The reference current generating circuit according to claim 1, wherein the plurality of second field effect transistors and the first switches are grouped into a plurality of units and the respective first switches commonly control the switching operation of the second field effect transistors in the respective units.