Synchronized media processing

• US 8,279,213 B2
• Filed: 12/23/2009
• Issued: 10/02/2012
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kaburlasos, Nikos, Sodhi, Inder M.
• Primary Examiner(s): Nguyen, Hau
• Application Number:
  US12/655,124
• Publication Number:
  US 20110148890A1
• Time in Patent Office: 1,014 Days
• Field of Search: 345211-213, 345502-504, 713300-340
• US Class Current: 345/211
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

Claims

1. A method to process media streams in an electronic device, comprising:

developing, in a power control unit in the electronic device, a predictive model of power states for a first processing unit in the electronic device; and

using the predictive model to synchronize activity of a second processing unit in the electronic device with periods of activity in the first processing unit, such that a processing activity of the second processing unit is suppressed in time periods in which the first processing unit is in a low power state, while maintaining a processing task executing on the second processing unit a processing rate that exceeds a predetermined threshold.

2. The method of claim 1, wherein developing, in a power control unit in the electronic device, a predictive model of power states for a first processing unit comprises:

initiating a video stream playback in the electronic device;

monitoring, in the power control unit, state transitions in the first processing unit during the video stream playback; and

using timing information associated with the state transitions to develop the predictive model of power states for the first processing unit.

3. The method of claim 1, wherein using the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the first processing unit comprises:

halting execution of the second processing unit during processing of a graphics frame; and

saving state information associated with the graphics frame.

4. The method of claim 3, further comprising:

monitoring, in the power control unit, a video processing rate of the second processing unit; and

activating the second processing unit when the video processing rate falls below a predetermined threshold.

5. The method of claim 1, wherein using the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the first processing unit further comprises:

activating the graphics processing unit when the first processing unit transitions from a low power state to an active state.

6. The method of claim 5, further comprising:

processing the video stream on the second processing unit; and

halting execution of the second processing unit when the predictive model indicates that the first processing unit is entering a low-power state.

7. The method of claim 1, wherein:

the first processing unit is activated on a periodic basis by a tick from an operating system which executes on the electronic device.

8. An apparatus, comprising logic to:

develop a predictive model of power states for a central processing unit;

use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit, such that a processing activity of the graphics processing unit is suppressed in time periods in which the central processing unit is in a low power state, while maintaining a processing task executing on the second processing unit a processing rate that exceeds a predetermined threshold.

9. The apparatus of claim 8, further comprising logic to:

initiate a video stream playback in the electronic device;

monitor, in the power control unit, state transitions in the central processing unit during the video stream playback; and

use timing information associated with the state transitions to develop the predictive model of power states for the central processing unit.

10. The apparatus of claim 8, further comprising logic to:

halt execution of the graphics processing unit during processing of a graphics frame; and

save state information associated with the graphics frame.

11. The apparatus of claim 8, further comprising logic to:

activate the graphics processing unit when the central processing unit transitions from a low power state to an active state.

12. The apparatus of claim 8, further comprising logic to:

process the video stream on the graphics processing unit; and

halt execution of the graphics processing unit when the predictive model indicates that the central processing unit is entering a low-power state.

13. The apparatus of claim 8, further comprising logic to:

monitor, in the power control unit, a video processing rate of the graphics processing unit; and

activate the graphics processing unit when the video processing rate falls below a predetermined threshold.

14. The apparatus of claim 8, wherein:

the central processing unit is activated on a periodic basis by a tick from an operating system.

23. The electronic device of claim 8, wherein the power control unit further comprises logic to:

initiate a video stream playback in the electronic device;

monitor, in the power control unit, state transitions in the central processing unit during the video stream playback; and

use timing information associated with the state transitions to develop the predictive model of power states for the central processing unit.

24. The electronic device of claim 8, wherein the power control unit further comprises logic to:

halt execution of the graphics processing unit during processing of a graphics frame; and

save state information associated with the graphics frame.

25. The electronic device of claim 8, wherein the power control unit further comprises logic to:

activate the graphics processing unit when the central processing unit transitions from a low power state to an active state.

15. A computer program product comprising logic instructions stored on a computer readable medium which, when executed by a processing device, configure the processor to process media streams in an electronic device by performing operations, comprising:

developing, in a power control unit in the electronic device, a predictive model of power states for a central processing unit in the electronic device; and

using the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit, such that a processing activity of the graphics processing unit is suppressed in time periods in which the central processing unit is in a low power state, while maintaining a processing task executing on the second processing unit a processing rate that exceeds a predetermined threshold.

16. The computer program product of claim 15, wherein developing, in a power control unit in the electronic device, a predictive model of power states for a central processing unit comprises:

initiating a video stream playback in the electronic device;

monitoring, in the power control unit, state transitions in the central processing unit during the video stream playback; and

using timing information associated with the state transitions to develop the predictive model of power states for the central processing unit.

17. The computer program product of claim 15, wherein using the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit comprises:

halting execution of the graphics processing unit during processing of a graphics frame; and

saving state information associated with the graphics frame.

18. The computer program product of claim 17, wherein using the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit further comprises:

activating the graphics processing unit when the central processing unit transitions from a low power state to an active state.

19. The computer program product of claim 18, further comprising:

processing the video stream on the graphics processing unit; and

halting execution of the graphics processing unit when the predictive model indicates that the central processing unit is entering a low-power state.

20. The computer program product of claim 17, further comprising:

monitoring, in the power control unit, a video processing rate of the graphics processing unit; and

activating the graphics processing unit when the video processing rate falls below a predetermined threshold.

21. The computer program product of claim 15, wherein:

the central processing unit is activated on a periodic basis by a tick from an operating system which executes on the electronic device.

22. An electronic device, comprising:

a central processing unit;

a graphics processing unit;

a power control unit comprising logic to;

develop a predictive model of power states for a central processing unit in the electronic device;

use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit, such that a processing activity of the graphics processing unit is suppressed in time periods in which the central processing unit is in a low power state, while maintaining a processing task executing on the second processing unit a processing rate that exceeds a predetermined threshold.