Universal three phase controllers for power converters

• US 8,279,647 B2
• Filed: 09/14/2010
• Issued: 10/02/2012
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Jin, Taotao, Smedley, Keyue
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): PHAM, EMILY P
• Application Number:
  US12/882,056
• Publication Number:
  US 20110032735A1
• Time in Patent Office: 749 Days
• Field of Search: 363/39, 363 44- 48, 363/82, 363/84, 363 87- 92, 363125-128
• US Class Current: 363/89
• CPC Class Codes: H02J 3/1842 wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/4233 using a bridge converter comprising active switches
• CPC Class Codes: H02M 7/2173 in a biphase or polyphase circuit arrangement H02M7/2176 takes precedence; voltage multipliers H02M7/25
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/53875 with analogue control of three-phase output
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02E 40/20 Active power filtering [APF]
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
• CPC Class Codes: Y10S 323/91 Two of three phases regulated

Abstract

The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter.

Claims

1. A control core configured to implement a control key equation to produce a plurality of drive signals for a three-phase two or three-level converter, having a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter;

wherein

a voltage signal V_m is used to multiply a sawtooth or triangular signal to form a scalable sawtooth or triangular signal; and

the sawtooth or triangular signal is input into two comparators to compare with two output signals from a signal adjustment unit, resulting in trailing edge, leading edge, or double edge signals Q_p and Q_n.

2. The control core in claim 1, wherein:

a combination of selected line current signals and reference signals are inputs to the signal adjustment unit;

a constant value is integrated by an integrator and then added to itself by an adder (subtractor);

an output from the adder (subtractor) is multiplied by the voltage signal V_m and is compared with two output signals from the signal adjustment unit using the two comparators;

two flip-flops are set by an arrival of a clock signal and reset by a change of state of output signals of the comparators, resulting in drive signals Q_p and Q_n; and

the integrator is reset any time after the flip-flops are reset and before the end of a next switching cycle.

3. The control core in claim 1, wherein:

a combination of selected line current signals and reference signals are inputs to the signal adjustment unit;

a voltage signal V_m is integrated by an integrator and then added to itself by an adder (subtractor);

an output signal from the adder (subtractor) is compared to the two output signals from the signal adjustment unit;

two flip-flops are set by an arrival of a clock signal and reset by a change of state of output signals from the comparators, resulting in drive signals Q_p and Q_n; and

the integrator is reset any time after the flip-flops are reset and before the end of a next switching cycle.

4. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising:

a first and a second pulse-width modulator; and

a reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein;

the first and second pulse-width modulators are each based on comparing a signal with a saw-tooth or triangle waveform;

two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the two current signals i_p and i_n are input to two input terminals of a first signal adjustment unit;

the two voltage signals v_p and v_n are input to two multipliers respectively and each is multiplied by a voltage signal V_m to form two scalable voltage signals (V_p*V_m) and (V_n*V_m);

the two scalable voltage signals (V_p*V_m) and (V_n*V_m) are input into two input terminals of a second signal adjustment unit;

output signals of the first and second signal adjustment units are combined by two adders (subtractors) respectively;

output signals from the two adders (subtractors) are compensated by two compensators respectively to produce two compensated output signals, each compensator having a function G_c(s); and

the two compensated output signals are compared with a sawtooth or triangular signal in order to produce leading edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Q_p and Q_n.

5. The control core in claim 4, wherein the first and the second pulse width modulators are each based on an integrator with reset.

6. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising:

a first and a second pulse-width modulator; and

a reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein;

two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the two voltage signals v_p and v_r, are input to two multipliers and each is multiplied by a voltage signal V_m to form scalable voltage signals (V_p*V_m) and (V_n*V_m);

the two scalable voltage signals (V_p*V_m) and (V_n*V_m) and the two current signals i_p and i_n are combined by two adders (subtractors);

output signals from the two adders (subtractors) are then input into two input terminals of a signal adjustment unit;

two output signals from the signal adjustment unit are compensated by a compensator having a function G_c(s) to produce two compensated signals; and

the two compensated signals are compared with a sawtooth or triangular signal in order to produce leading edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Q_p and Q_n.

7. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising:

a first and a second pulse-width modulator; and

a reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein;

two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the two voltage signals v_p and v_n are input to two multipliers and each is multiplied by a voltage signal V_m to form scalable voltage signals (V_p*V_m) and (V_n*V_m);

the two scalable voltage signals (V_p*V_m) and (V_n*V_m) are input into two input terminals of a signal adjustment unit to produce two output signals that are respectively sent to two comparators;

a clock generates a clock signal, which is used to generate a synchronized sawtooth signal;

the i_p and i_n signals are input to a signal adjustment unit having two output signals, and the two output signals are linearly combined with the sawtooth signal and sent to the two comparators; and

flip-flops are set by an arrival of the clock signal and reset by a change of state of the comparators, resulting in output signals Q_p and Q_n.

8. A control core within a three-phase controller configured to implement a control key equation to produce a plurality of drive signals for a two or three-level converter, comprising:

a first and a second pulse-width modulator; and

a reference signal selection unit that is adjustable to allow the controller to control any one of a PFC, APF, VAR, or GCI converter, wherein;

two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the two voltage signals v_p and v_n are input to two multipliers and each is multiplied by a voltage signal V_m to form scalable voltage signals (V_p*V_m) and (V_n*V_m);

the two scalable voltage signals (V_p*V_m) and (V_n*V_m) are input into a first signal adjustment unit, the first signal adjustment unit outputting signals to a first set of input terminals of a Schmidt trigger;

the i_p and i_n signals are input to a second signal adjustment unit having two cross coupled amplifiers and two adders, the second signal adjustment unit outputting signals to a second set of input terminals of the Schmidt trigger; and

the Schmidt trigger generates variable frequency output signals Q_p and Q.

9. A control core, comprising:

a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; and

an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is;

10. A control core, comprising:

a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; and

an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is;

11. A control core, comprising:

a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; and

an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is

12. A control core, comprising:

a reference signal selection unit that is adjustable to allow for the control of any one of a PFC, APF, VAR, or GCI converter; and

an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is