Memory system with data line switching scheme

• US 8,279,650 B2
• Filed: 09/20/2009
• Issued: 10/02/2012
• Est. Priority Date: 04/20/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Yan, Tianhong, Fasoli, Luca
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Norman, James G
• Application Number:
  US12/563,139
• Publication Number:
  US 20100265750A1
• Time in Patent Office: 1,108 Days
• Field of Search: None
• US Class Current: 365/51
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.

Claims

1. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements;

one or more control circuits that perform memory operations; and

a first set of selection circuits, each selection circuit of the first set of selection circuits is in communication with the one or more control circuits and a different group of two or more of the non-volatile storage elements, during concurrent memory operations each of the selection circuits of the first set of selection circuits selectively and concurrently connect a respective first non-volatile storage element of respective groups to the one or more control circuits until the memory operation completes for the first non-volatile storage element of the respective groups and then selectively connect a second non-volatile storage element of the respective groups to the one or more control circuits-independently of the completion of the memory operation for the first non-volatile storage element of other groups, the first non-volatile storage element of each of the groups are all in a common block of non-volatile storage elements.

3. The non-volatile storage device of claim 1, wherein:

when the respective first non-volatile storage element of a group of non-volatile storage elements is connected to the one or more control circuits, the one or more control circuits SET the resistance of the respective first non-volatile storage element of the group by discharging a charge through the respective first non-volatile storage element of the group.

4. The non-volatile storage device of claim 1, further comprising:

control lines in communication with the non-volatile storage elements, the non-volatile storage elements are arranged as sets of non-volatile storage elements;

multiple sets of local data lines, each set of non-volatile storage elements includes its own set of local data lines;

a set of global data lines, the control circuits are in communication with the global data lines; and

a second set of selection circuits, each set of non-volatile storage elements includes a different subset of the second set of selection circuits for selectively connecting a subset of the control lines to local data lines for the respective set of non-volatile storage elements, the first set of selection circuits selectively connect the local data lines to the global data lines.

5. The non-volatile storage device of claim 4, wherein:

each selection circuit of the first set of selection circuits is in communication with a different group of two or more of the local data lines and one of the global data lines so that during concurrent memory operations each selection circuit of the first set of selection circuits selectively connects a respective first local data line to one global data line until the memory operation completes for the first non-volatile storage element of the groups and then selectively connects a second local data line to the one global data line independent of other selection circuits of the first set of selection circuits.

6. The non-volatile storage device of claim 5, wherein:

the one or more control circuits include sense amplifier circuits;

the sense amplifier circuits determine, independently for each non-volatile storage element being monitored, that the memory operation completes and outputs a signal in response to determining that the memory operation completes; and

the first set of selections circuits include multiplexer circuits that each receive and switch connections between local data lines in response to the signal from one of the sense amplifier circuits.

7. The non-volatile storage device of claim 4, wherein:

when the respective first non-volatile storage element of a group non-volatile storage elements is connected to the one or more control circuits, the one or more control circuits SET the resistance of the respective first non-volatile storage element of the group by discharging a capacitive charge through the respective first non-volatile storage element of the group.

8. The non-volatile storage device of claim 4, wherein:

the control lines are positioned within the plurality of non-volatile storage elements;

the local data lines are outside the plurality of non-volatile storage element; and

the global data lines are positioned outside of the plurality of non-volatile storage elements.

9. The non-volatile storage system of claim 8, wherein:

the local data lines are positioned in at least one metal layer below the plurality of non-volatile storage elements; and

the global data lines are positioned in at least one metal layer above the plurality of non-volatile storage elements.

10. The non-volatile storage system of claim 9, wherein:

the control circuitry is positioned on a surface of a substrate;

the plurality of non-volatile storage elements comprise a monolithic three-dimensional memory array positioned above the surface of the substrate and above the control circuitry;

the local data lines are positioned between the monolithic three-dimensional memory array and the surface of the substrate; and

the global data lines are positioned above the monolithic three-dimensional memory array and the surface of the substrate.

11. The non-volatile storage system of claim 1, wherein:

the control circuitry is positioned on a surface of a substrate; and

the plurality of non-volatile storage elements comprise a monolithic three-dimensional memory array positioned above the surface of the substrate and above the control circuitry.

12. The non-volatile storage system of claim 1, wherein:

each non-volatile storage elements of the plurality of non-volatile storage elements includes a reversible resistance-switching element.

2. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements;

one or more control circuits that perform memory operations, the one or more control circuits include sense amplifier circuits; and

a first set of selection circuits, each selection circuit of the first set of selection circuits is in communication with the one or more control circuits and a different group of two or more of the non-volatile storage elements, during concurrent memory operations each of the selection circuits of the first set of selection circuits selectively and concurrently connect a respective first non-volatile storage element of respective groups to the one or more control circuits until the memory operation completes for the first non-volatile storage element of the respective groups and then selectively connect a second non-volatile storage element of the respective groups to the one or more control circuits-independently of the completion of the memory operation for the first non-volatile storage element of other groups;

the sense amplifier circuits determine, independently for each non-volatile storage element being monitored, that the memory operation completes and outputs a signal in response to determining that the memory operation completes; and

the first set of selections circuits include multiplexer circuits that each receive the signal from one of the sense amplifier circuits and switch connections from the first non-volatile storage element of the group to the second non-volatile storage element of the group.

13. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements, the plurality of non-volatile storage elements includes multiple subsets of non-volatile storage elements;

control lines in communication with the non-volatile storage elements;

local data lines, each subset of non-volatile storage elements includes its own set of local data lines;

a set of global data lines for the multiple subsets of non-volatile storage elements;

first selection circuits, the first selection circuits selectively connect a subset of the local data lines to the global data lines;

second selection circuits that selectively connecting a subset of the control lines to the first local data lines; and

control circuits in communication with the global data lines, each selection circuit of the first set of selection circuits is in communication with a different group of two or more of the local data lines and one global data line, during concurrent memory operations each of the selection circuits of the first set of selection circuits selectively and concurrently connect a respective first local data line to a respective global data line until the memory operation completes for the respective first local data line and then selectively and concurrently connect a respective second local data line to the respective global data line independently of the completion of the memory operation for the first local data lines of other groups.

14. The non-volatile storage device of claim 13, wherein:

the first set of selections circuits include multiplexer circuits each of which is connected to two or more local data lines and one global data line.

15. The non-volatile storage device of claim 13, wherein:

the control lines are positioned within the plurality of non-volatile storage elements;

the local data lines are outside the plurality of non-volatile storage element; and

the global data lines are positioned outside of the plurality of non-volatile storage elements.

16. The data storage system of claim 15, wherein:

the local data lines are positioned in at least one metal layer below the plurality of non-volatile storage elements; and

the global data lines are positioned in at least one metal layer above the plurality of non-volatile storage elements.

17. The data storage system of claim 13, wherein:

the control circuitry is positioned on a surface of a substrate;

the plurality of non-volatile storage elements comprise a monolithic three-dimensional memory array positioned above the surface of the substrate and above the control circuitry;

the local data lines are positioned between the monolithic three-dimensional memory array and the surface of the substrate; and

the global data lines are positioned above the monolithic three-dimensional memory array and the surface of the substrate.

18. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements;

one or more control circuits that perform memory operations, the one or more control circuits include sense amplifier circuits, the sense amplifier circuits determine independently for each non-volatile storage element being monitored that the memory operation completes and outputs a signal in response to determining that the memory operation completes; and

a first set of selection circuits, each selection circuit of the first set of selection circuits is in communication with and receives the signal from one of the sense amplifiers, each selection circuit of the first set of selection circuits is in communication with a different group of two or more of the non-volatile storage elements so that during memory concurrent operations each selection circuit of the first set of selection circuits selectively and concurrently connects a respective first non-volatile storage element of the group to the one or more control circuits until a memory operation completes for the respective first non-volatile storage element of the group and then selectively connects a respective second non-volatile storage element of the group to the one or more control circuits independent of other selection circuits of the first set of selection circuits switching connection from the first non-volatile storage element to the second non-volatile storage element for their respective groups, the first set of selections circuits switch connections from the first non-volatile storage element to the second non-volatile storage element for their respective groups in response to the respective signal from the respective sense amplifier.