Memory chip package with efficient data I/O control

• US 8,279,651 B2
• Filed: 06/29/2010
• Issued: 10/02/2012
• Est. Priority Date: 06/29/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Seong, Jin Yong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/826,518
• Publication Number:
  US 20100329042A1
• Time in Patent Office: 826 Days
• Field of Search: 365/51, 365/52, 365/189.05, 365/226, 365/230.03, 365/230.06
• US Class Current: 365/51
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.

Claims

1. A memory chip, comprising:

a memory circuit unit configured to include memory cells for storing data;

a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip;

a plurality of driver control units, each of which is configured to generate a driver addition signal to enable corresponding one of the data I/O buffer circuits when a power supply voltage has been received; and

a controller configured to generate I/O enable signals for controlling an operation of the data input and output I/O buffer unit.

2. The memory chip of claim 1, wherein the data input and output I/O buffer unit comprises:

an output buffer unit comprising a plurality of output buffer circuits, each enabled in response to an output enable signal received through an I/O node wired to an external data I/O package lead and configured to output the data received from the memory circuit unit to an I/O pad; and

an input buffer unit coupled to the I/O pad and configured to include a plurality of input buffer circuits, each enabled in response to the input enable signal and configured to output data received from the I/O pad to the memory circuit unit.

3. The memory chip of claim 2, wherein each of the driver control units comprises:

a buffer comprising an input terminal and an output terminal, wherein the buffer is configured to determine a logic level of the driver addition signal corresponding to a voltage level of a signal received through the input terminal so as to determine an operation of a corresponding one of the data I/O buffer circuits, and wherein the buffer is configured to output the driver addition signal having a voltage having a logic level through the output terminal; and

a default setting unit configured to couple the input terminal of the buffer to a ground node so that, in an initial operation, the driver addition signal is fixed to a first logic level,

wherein in a case in which the input terminal is wired to the data I/O package lead, the driver addition signal is fixed to a second logic level irrespective of a connection of the default setting unit.

4. The memory chip of claim 3, wherein the default setting unit comprises:

a first transistor turned on by the power supply voltage; and

a plurality of second transistors turned on by the power supply voltage received through the first transistor,

wherein when the second transistors are turned on, the ground node and the input terminal of the buffer are coupled together.

5. The memory chip of claim 4, wherein the default setting unit further comprises:

a first resistor coupled between the first transistor and a terminal through which the power supply voltage is received; and

a second resistor coupled between the second transistors and the input terminal of the buffer.

6. A memory chip package including one or more memory chips, each of the memory chips comprising:

a memory circuit unit configured to include memory cells for storing data;

a data I/O buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip;

a plurality of driver control units, each of which is configured to generate a driver addition signal to enable corresponding one of the data I/O buffer circuits when a power supply voltage has been received; and

a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.

7. The memory chip package of claim 6, wherein each of the driver control units comprises:

a buffer comprising an input terminal and an output terminal, wherein the buffer is configured to determine a logic level of the driver addition signal corresponding to a voltage level of a signal received through the input terminal so as to determine an operation of a corresponding one of the data I/O buffer circuits, and wherein the buffer is configured to output the driver addition signal having a voltage having a logic level through the output terminal; and

a default setting unit configured to couple the input terminal of the buffer to a ground node so that, in an initial operation, the driver addition signal is fixed to a first logic level,

wherein in a case in which the input terminal is wired to the data I/O package lead, the power supply voltage is supplied to the input terminal so that the driver addition signal is fixed to a second logic level irrespective of a connection of the default setting unit.

8. The memory chip package of claim 7, wherein the default setting unit comprises:

a first transistor turned on by the power supply voltage; and

a plurality of second transistors turned on by the power supply voltage received through the first transistor,

wherein when the second transistors are turned on, the ground node and the input terminal of the buffer are coupled together.

9. The memory chip package of claim 8, wherein the default setting unit further comprises:

a first resistor coupled between the first transistor and a terminal through which the power supply voltage is received; and

a second resistor coupled between the second transistors and the input terminal of the buffer.