Memory chip package with efficient data I/O control
First Claim
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1. A memory chip, comprising:
- a memory circuit unit configured to include memory cells for storing data;
a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip;
a plurality of driver control units, each of which is configured to generate a driver addition signal to enable corresponding one of the data I/O buffer circuits when a power supply voltage has been received; and
a controller configured to generate I/O enable signals for controlling an operation of the data input and output I/O buffer unit.
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Abstract
A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.
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Citations
9 Claims
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1. A memory chip, comprising:
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a memory circuit unit configured to include memory cells for storing data; a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip; a plurality of driver control units, each of which is configured to generate a driver addition signal to enable corresponding one of the data I/O buffer circuits when a power supply voltage has been received; and a controller configured to generate I/O enable signals for controlling an operation of the data input and output I/O buffer unit. - View Dependent Claims (2, 3, 4, 5)
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6. A memory chip package including one or more memory chips, each of the memory chips comprising:
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a memory circuit unit configured to include memory cells for storing data; a data I/O buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip; a plurality of driver control units, each of which is configured to generate a driver addition signal to enable corresponding one of the data I/O buffer circuits when a power supply voltage has been received; and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit. - View Dependent Claims (7, 8, 9)
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Specification