Single supply sub VDD bit-line precharge SRAM and method for level shifting

• US 8,279,687 B2
• Filed: 05/13/2010
• Issued: 10/02/2012
• Est. Priority Date: 05/13/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Adams, Chad A., Braceras, George M., Pilo, Harold, Ramadurai, Vinod, Nelson, Daniel M
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US12/779,608
• Publication Number:
  US 20110280088A1
• Time in Patent Office: 873 Days
• Field of Search: 365/189.11, 365/189.09, 365/203, 365/226, 365/227, 365/230.06, 365/189.07, 365/154, 365/156
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.

Claims

1. A pre-charge bit-line circuit for a static random access memory (SRAM) having a plurality of read/write sense amplifiers, and drivers comprising:

a regulated power supply source providing a reference voltage less than Vdd;

a bias circuit having a regulator circuit connected to the power supply and a distributed regulator that is connected to the bit-lines; and

a level shifting circuit providing a bit-line control signal to activate the bit-line to a full Vdd voltage and return the bit-lines to the reference voltage level.

2. The pre-charge circuit of claim 1 wherein the regulator circuit includes a leakage compensation circuit that prevents the distributed regulator from rising above the reference voltage.

3. The pre-charge circuit of claim 2 wherein the regulator circuit is a push-pull device.

4. The pre-charge circuit of claim 3 wherein the distributed regulator further is a self-compensating body connected device.

5. The pre-charge circuit of claim 4 wherein the self-compensating body connected device is a diode-connected PFET to compensate the reference level to the bit-lines.

6. The pre-charge circuit of claim 1 wherein level shifting includes a first sense amplifier and write drivers for level shifting the sense amplifiers from the reference level to full Vdd voltage.

7. The pre-charge circuit of claim 6 include a second sense amplifier returning the bit-lines to the reference voltage.

8. A pre-charge bit-line circuit for a static random access memory (SRAM) having a plurality of read/write sense amplifiers, and drivers comprising:

a regulated power supply source providing a reference voltage less than Vdd;

a bias circuit having a regulator circuit connected to the power supply and a self-compensating body connected device is connected to the bit-lines;

a level shifting circuit having a first sense amplifier and write drivers for level shifting the sense amplifiers from the reference level to full Vdd and a second sense amplifier returning the bit-lines to the reference voltage.

9. The pre-charge circuit of claim 8 wherein the self-compensating body connected device is a diode-connected PFET to compensate the reference level to the bit-lines.

10. The pre-charge circuit of claim 9 wherein the regulator circuit is a push-pull device.

11. The pre-charge circuit of claim 10 wherein the regulator circuit includes a leakage compensation circuit that prevents the distributed regulator from rising above the reference voltage.

12. The pre-charge circuit of claim 11 includes logic circuits to apply Vdd voltages to sense amplifier circuits.

13. The pre-charge circuit of claim 12 includes logic circuits to apply reference voltage to bit-lines restore and sense amplifier restore.

14. A method for pre-charging a bit-line circuit in a static random access memory (SRAM) having a plurality of read/write sense amplifiers, and drivers comprising the steps of;

providing a reference voltage source less than Vdd;

regulating the reference voltage source;

biasing the reference voltage source;

compensating the reference voltage supplied to the bit-lines;

generating a first control signal for level shifting and activating a bit-line to a full Vdd voltage; and

later generating a second control signal to return the bit-line to the reference voltage.

15. The method for pre-charging a bit-line circuit of claim 14 including a step of adjusting the reference voltage for leakage.

16. The method for pre-charging a bit-line circuit of claim 15 wherein the step of adjusting the reference voltage for leakage prevents the reference voltage to the bit-lines from rising above the reference voltage.

17. The method for pre-charging a bit-line circuit of claim 16 using a push-pull system for level shifting.

18. The method for pre-charging a bit-line circuit of claim 17 connecting the reference to body of a PFET diode for self-compensating the reference voltage.

19. The method for pre-charging a bit-line circuit of claim 18 wherein the step of generating a first control signal for level shifting includes a sense amplifier and a write driver.

20. The pre-charge circuit of claim 19 wherein the step of generating a second control signal level shifting includes a first sense amplifier and write driver.