Multiple-channel software defined radios and systems using the same

• US 8,279,796 B1
• Filed: 11/16/2007
• Issued: 10/02/2012
• Est. Priority Date: 11/16/2007
• Status: Active Grant

• Current Assignee: MeteorComm LLC (Berkshire Hathaway Incorporated)
• Original Assignee: BNSF Railway Company (Berkshire Hathaway Incorporated)
• Inventors: Cleveland, John F., Donich, Thomas G.
• Primary Examiner(s): Hamza, Faruk
• Assistant Examiner(s): CRUTCHFIELD, CHRISTOPHER M
• Application Number:
  US11/985,764
• Time in Patent Office: 1,782 Days
• Field of Search: 375/326, 455/418, 711/101, 710/100
• US Class Current: 370/319
• CPC Class Codes: H04B 1/0035 Channel filtering, i.e. selecting a frequency channel within a software radio system multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/26 Systems using multi-frequency codes H04L27/32 takes precedence
• CPC Class Codes: H04L 5/06 the signals being represented by different frequencies combined with time-division multiplexing H04L5/26
• CPC Class Codes: H04W 56/0045 compensating for timing error by altering transmission time

Abstract

A radio system including a selected number inputs for substantially simultaneously receiving radio signals in different frequency bands and a selected number of conversion paths for converting the radio signals received at corresponding ones of the inputs into a corresponding number of digital streams. Digital processing circuitry substantially simultaneously processes digital samples for plurality of channels, the samples taken from at least one of the digital streams, wherein a maximum number of channels is greater than a maximum number of digital streams provided by the conversion paths.

Claims

1. A radio system comprising:

a selected number of inputs for substantially simultaneously receiving radio signals in different frequency bands;

a selected number of conversion paths for converting the radio signals received at corresponding ones of the inputs into a corresponding number of digital streams;

a plurality of digital processing circuits implemented on a field programmable gate array for substantially simultaneously processing digital samples for a plurality of channels, the samples for each channel taken from a selected one of the digital streams, wherein a maximum number of channels is greater than a maximum number of digital streams, each digital processing circuit comprising;

mixing circuitry for generating digital in-phase and quadrature sample streams from the samples for a corresponding channel;

gain control circuitry for setting gain for the in-phase and quadrature sample streams;

digital filtering circuitry for filtering the digital in-phase and quadrature sample streams, the digital filtering circuitry comprising;

comb filters for filtering and decimating the in-phase and quadrature sample streams output from the mixing circuitry; and

low pass finite impulse response filters for filtering and decimating the filtered in-phase and quadrature sample streams output from the comb filters; and

Cartesian to polar rotation and phase differentiation circuitry for generating magnitude, phase, and instantaneous frequency information from the in-phase and quadrature sample streams;

switching circuitry for switching the samples for each of the channels from a selected one of the digital streams to the corresponding data processing circuit; and

a digital signal processor for demodulating a selected one of the in-phase and quadrature sample stream and the magnitude, phase, and instantaneous frequency information from a selected one of the plurality of digital processing circuits, wherein the digital signal processor selects between the in-phase and quadrature sample stream and the magnitude, phase, and instantaneous frequency information based on a modulation type of digital samples of the channel being processed by the selected one of the digital processing circuits, the digital signal processor selecting blocks of instantaneous frequency, magnitude, and phase information when the modulation type of the channel being demodulated comprises Gaussian Mean Shift Keying.

2. The radio system of claim 1, wherein:

the inputs are operable to receive radio signals on low, high, and ultra high receive frequency bands;

the conversion paths are operable to generate first, second, and third digital streams in response to radio signals respectively received on the low, high, and ultra high frequency bands; and

the plurality of digital processing circuits comprise at least four digital processing circuits each operable to process samples for a corresponding one of at least four channels.

3. A digital radio comprising:

analog to digital conversion circuitry for substantially simultaneously converting radio signals received on plurality of frequency bands into a plurality of sample streams; and

a field programmable gate array comprising first and second processing paths for substantially simultaneously processing samples for first and second channels, the samples taken from at least one of the plurality of sample streams, wherein a maximum number of sample streams is less than a maximum number of channels and each of the first and second processing paths includes;

mixing circuitry for generating streams of in-phase and quadrature samples for the associated channel;

gain control circuitry for controlling gain of the streams of in-phase and quadrature samples;

digital filtering circuitry for filtering each of the streams of in-phase and quadrature samples comprising;

a comb filter for filtering and decimating the in-phase and quadrature sample streams output from the mixing circuitry; and

a low pass finite impulse response filters for filtering and decimating the filtered in-phase and quadrature sample streams output from the comb filters; and

Cartesian to polar rotation and phase differentiation circuitry for generating instantaneous frequency, magnitude, and phase information; and

a digital signal processor for demodulating blocks of output information generated for each of the first and second channels by the first and second digital processing paths, the blocks of output information selected from the group consisting of blocks of in-phase and quadrature information and blocks of instantaneous frequency, magnitude, and phase information, wherein the digital signal processor selects between the blocks of in-phase and quadrature information and the blocks of instantaneous frequency, magnitude, and phase information based on a modulation type of the channel being demodulated, the digital signal processor selecting the blocks of instantaneous frequency, magnitude, and phase information when the modulation type of the channel being demodulated comprises Gaussian Mean Shift Keying.

4. The digital radio of claim 3, wherein the digital filtering circuitry includes at least one filter selected from the group consisting of comb filters and a finite impulse response filters.

5. The digital radio of claim 3, further comprising:

a transmit processing path within field programmable gate array for processing digital data being transmitted by the radio; and

direct digital synthesis circuitry for converting digital transmit data output from the field programmable gate array into analog form for transmission on a selected one of a plurality of radio frequency transmit bands.

6. The digital radio of claim 5, wherein the transmit processing path within the field programmable gate array comprises a finite impulse response filter for interpolating and filtering the transmit data.

7. The digital radio of claim 5, further comprising a digital signal processor for modulating the digital data being transmitted by the radio and delivering modulated data to the transmit processing path within the field programmable gate array.

8. A software defined digital radio system comprising:

a digital signal processor for demodulating sample blocks for a plurality of receive channels received on at least one selected frequency band, the sample blocks selected from the group consisting of blocks of in-phase and quadrature samples and blocks of, magnitude, phase, and instantaneous frequency samples;

a field programmable gate array including;

buffering circuitry for storing sample blocks for the receive channels being demodulated by the digital signal processor; and

a plurality of receive processing paths each for processing input samples and in response generating for storage in the buffering circuitry the sample blocks for a corresponding one of the receive channels, each receive processing path including;

mixing circuitry for mixing the corresponding data samples with a local oscillator to generate in-phase and quadrature sample streams;

gain control circuitry for setting gain for the in-phase and quadrature sample streams output from the mixing circuitry;

a comb filter for filtering and decimating the in-phase and quadrature sample streams generated by the mixing circuitry after setting the gain;

a low pass finite impulse response filter for filtering and decimating the filtered in-phase and quadrature sample streams generated by the comb filters; and

rotation and phase differentiation circuitry for generating magnitude, phase, and instantaneous frequency information from the filtered in-phase and quadrature sample streams generated by the low pass finite impulse response filters;

input switching circuitry for switching input data samples from at least one input sample stream to the plurality of receive processing paths;

analog to digital conversion circuitry for generating the at least one input sample stream from an analog input signal received on the at least one selected input radio frequency band, wherein the input switching circuitry and a number of the receive processing paths allows the sample blocks of the plurality of channels to be extracted from the at least one input sample stream and such that a maximum number of the receive channels processed by the digital signal processor is greater than a maximum number of digital streams generated by the analog to digital conversion circuitry; and

wherein the digital signal processor selects between the blocks of in-phase and quadrature samples and the blocks of magnitude, phase, and instantaneous frequency samples based on a modulation type of the receive channel being demodulated, the digital signal processor selecting the blocks of magnitude, phase, and instantaneous frequency samples when the modulation type of the receive channel being demodulated comprises Gaussian Mean Shift Keying.

9. The software defined radio of claim 8, wherein:

the input switching circuitry is operable to substantially simultaneously switch input samples from a plurality of input streams to the plurality of receive processing paths; and

the analog to digital conversion circuitry is operable to substantially simultaneously generate the plurality of input streams from a plurality of analog input signals of a plurality of selected input radio frequency bands.

10. The software defined radio of claim 8, wherein the digital signal processor is further operable to modulate data sample blocks for a transmit channel and the field programmable gate array further comprises:

buffering circuitry for storing modulated data sample blocks from the digital signal processor; and

a transmit path for processing transmit data samples from the modulated sample blocks stored in the buffering circuitry for the transmit channel.

11. The software defined radio of claim 10, wherein the transmit path of the field programmable gate array comprises a finite impulse response filter for filtering and interpolating the transmit data samples.