Distributed digital signal processor
First Claim
1. A distributed digital signal processor (DSP) comprises:
- an instruction memory that stores a plurality of instructions;
a data memory that stores a plurality of data elements;
a multiply-accumulate module that performs a function upon first and second data elements of the plurality of data elements in accordance with a command of an instruction of the plurality of instructions to produce a resultant;
an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver;
retrieves an instruction from the instruction memory;
interprets the instruction to identify a function from a plurality of functions, an address of the first data element, and an address of the second data element;
converts a command corresponding to the function into a command symbol stream;
converts the addresses of the first and second data elements into an addressed data symbol stream;
converts the command symbol stream into a MMW command signal; and
converts the addressed data symbol stream into a MMW addressed data signal, the MMW command signal and the MMW data signal forming a MMW instruction signal; and
transmits a the MMW instruction signal that includes at least a portion of the instruction;
a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements; and
a multiply-accumulate MMW transceiver coupled to the multiply-accumulate module, wherein the multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal; and
a control unit operable to;
identify the instruction based on execution of an algorithm;
generate a retrieve instruction request for the instruction based on the execution of the algorithm;
identify the first and second data elements; and
generate a retrieve data request for the first and second data elements;
a control MMW transceiver coupled to;
convert the retrieve instruction request into a MMW retrieve instruction signal, wherein the instruction MMW transceiver transmits the MMW instruction signal in response to receiving the MMW retrieve instruction signal; and
convert the retrieve data request into a MMW data request signal, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW retrieve data signal.
4 Assignments
0 Petitions
Accused Products
Abstract
A distributed digital signal processor (DSP) includes instruction memory, data memory, a multiply-accumulate module, an instruction MMW transceiver, a data MMW transceiver, and a multiply-accumulate transceiver. The multiply-accumulate module performs a function upon first and second data elements in accordance with a command of an instruction. The instruction MMW transceiver transmits a MMW instruction signal that includes at least a portion of the instruction. The data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements. The multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal.
99 Citations
20 Claims
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1. A distributed digital signal processor (DSP) comprises:
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an instruction memory that stores a plurality of instructions; a data memory that stores a plurality of data elements; a multiply-accumulate module that performs a function upon first and second data elements of the plurality of data elements in accordance with a command of an instruction of the plurality of instructions to produce a resultant; an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver; retrieves an instruction from the instruction memory; interprets the instruction to identify a function from a plurality of functions, an address of the first data element, and an address of the second data element; converts a command corresponding to the function into a command symbol stream; converts the addresses of the first and second data elements into an addressed data symbol stream; converts the command symbol stream into a MMW command signal; and converts the addressed data symbol stream into a MMW addressed data signal, the MMW command signal and the MMW data signal forming a MMW instruction signal; and transmits a the MMW instruction signal that includes at least a portion of the instruction; a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW instruction signal, wherein the MMW data signal includes the first and second data elements; and a multiply-accumulate MMW transceiver coupled to the multiply-accumulate module, wherein the multiply-accumulate MMW transceiver recovers the first and second data elements from the MMW data signal and recovers a command corresponding to the function from the MMW instruction signal; and a control unit operable to; identify the instruction based on execution of an algorithm; generate a retrieve instruction request for the instruction based on the execution of the algorithm; identify the first and second data elements; and generate a retrieve data request for the first and second data elements; a control MMW transceiver coupled to; convert the retrieve instruction request into a MMW retrieve instruction signal, wherein the instruction MMW transceiver transmits the MMW instruction signal in response to receiving the MMW retrieve instruction signal; and convert the retrieve data request into a MMW data request signal, wherein the data MMW transceiver transmits a MMW data signal in response to receiving the MMW retrieve data signal. - View Dependent Claims (2, 3, 4)
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5. A distributed digital signal processor (DSP) comprises:
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an instruction memory that stores a plurality of instructions; a data memory that stores a plurality of data elements; an arithmetic module that performs an arithmetic function upon a product of first and second data elements of the plurality of data elements in accordance with an instruction of the plurality of instructions to produce a resultant; an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes the instruction; a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver includes; a baseband processing module coupled to; receive the first and second data elements from the data memory; convert the first data element into a first data symbol stream; and convert the second data element into a second data symbol stream; an up conversion mixing module coupled to; mix the first data symbol stream, the second data symbol stream, and a transmit local oscillation in accordance with a multiply function of the instruction to produce a multiplied mixed signal that includes the product of first and second data elements; wherein the up conversion mixing module comprises a first multiplier, a second multiplier, a first filter, a second filter, a second power amplifier module, and a multiplexer coupled to the first and second multipliers, wherein; in accordance with the multiply function of the instruction;
the multiplexer provides the second data symbol stream to the first multiplier;
the first multiplier multiplies the first data symbol stream, the second data symbol stream, and the transmit local oscillation to produce an intermediate product; and
the first filter module coupled to filter the intermediate product to produce the multiplied mixed signal; and
in accordance with a data request of the instruction;
the multiplexer provides the second data symbol stream to the second multiplier;
the first multiplier multiplies the first data symbol stream and the transmit local oscillation to produce a first mixed signal; and
the first filter module coupled to filter the first mixed signal to produce a first MMW data signal;the second multiplier multiplies the second data symbol stream and the transmit local oscillation to produce a second mixed signal; the second filter module coupled to filter the second mixed signal to produce a second MMW data signal; the second power amplifier amplifies the second MMW data signal; a power amplifier module coupled to amplify the multiplied mixed signal to produce a MMW data product signal; and an arithmetic MMW transceiver coupled to the arithmetic module, wherein the arithmetic MMW transceiver recovers the product of first and second data elements from the MMW data product signal and recovers the command corresponding to the arithmetic function from the MMW instruction signal. - View Dependent Claims (6, 7, 8, 9)
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10. A distributed digital signal processor (DSP) comprises:
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an instruction memory that stores a plurality of instructions; a data memory that stores a plurality of data elements; an arithmetic module that performs an arithmetic function upon a product of first and second data elements of the plurality of data elements in accordance with an instruction of the plurality of instructions to produce a resultant; an instruction millimeter wave (MMW) transceiver coupled to the instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes the instruction; a data MMW transceiver coupled to the data memory, wherein the data MMW transceiver transmits a first MMW data signal and second MMW data signal in response to receiving the MMW instruction signal, wherein the first MMW data signal includes the first data element and the second MMW data signal includes the second data element; and an arithmetic MMW transceiver coupled to the arithmetic module, wherein the arithmetic MMW transceiver includes; a low noise amplifier section coupled to; amplify the MMS instruction signal to produce an amplified MMW instruction signal; amplify the first MMW data signal to produce a first amplified MMW data signal; and amplify the second MMW data signal to produce a second amplified MMW data signal; a down conversion section coupled to; convert the amplified MMW instruction signal into an instruction symbol stream; and mix the first amplified MMW data signal, the second amplified MMW data signal, and a receive local oscillation to produce a mixed down converted signal in accordance with a multiply command; and a baseband processing module coupled to; recover the command and the multiply command from the instruction symbol stream; convert the mixed down converted signal into the product of first and second data elements; and provide the product of the first and second data elements to the arithmetic module. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A distributed digital signal processor (DSP) comprises:
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a data MMW transceiver coupled to a data memory, wherein the data memory stores a plurality of data elements; an instruction millimeter wave (MMW) transceiver coupled to an instruction memory, wherein the instruction MMW transceiver transmits a MMW instruction signal that includes an instruction stored in the instruction memory; an arithmetic module that performs an arithmetic function upon a product of first and second data elements of the plurality of data elements in accordance with the instruction to produce a resultant; wherein the data MMW transceiver includes; a baseband processing module coupled to; receive the first and second data elements from the data memory; convert the first data element into a first data symbol stream; and convert the second data element into a second data symbol stream; an up conversion mixing module coupled to; mix the first data symbol stream, the second data symbol stream, and a transmit local oscillation in accordance with a multiply function of the instruction to produce a multiplied mixed signal that includes the product of first and second data elements; and to produce a MMW data product signal with the product of the first and second data elements; an arithmetic MMW transceiver coupled to the arithmetic module, wherein the arithmetic MMW transceiver recovers the product of first and second data elements from the MMW data product signal and recovers the command corresponding to the arithmetic function from the MMW instruction signal. - View Dependent Claims (17, 18, 19, 20)
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Specification