Direct fault diagnostics using per-pattern compactor signatures
First Claim
Patent Images
1. A method of testing an electronic circuit comprising:
- receiving a signature from a time compactor associated with the electronic circuit;
determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor; and
storing the list of initial candidate fault locations on one or more computer readable media.
2 Assignments
0 Petitions
Accused Products
Abstract
In embodiments of the disclosed technology, diagnosis of a circuit is performed using compactor signatures (a technique referred to herein as “signature-based diagnosis”). Signature-based diagnosis typically does not require a test step that bypasses the compactor. Compactor signatures can be read from a compactor on a per-pattern basis, and an expected signature can be loaded into a compactor while an actual signature is being read from the compactor. Error functions can be used to describe relationships between errors in scan cell values and per-pattern compactor signatures, and the functions can be used to help generate a list of fault candidates in a circuit design.
75 Citations
45 Claims
-
1. A method of testing an electronic circuit comprising:
-
receiving a signature from a time compactor associated with the electronic circuit; determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor; and storing the list of initial candidate fault locations on one or more computer readable media. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A circuit having a repaired fault that was identified using a method, the method comprising:
-
receiving a signature from a time compactor associated with an electronic circuit; determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor; storing the list of initial candidate fault locations on one or more computer readable media; and performing one or more fault simulations to determine a revised list of fault locations from the list of initial candidate fault locations.
-
-
11. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer to perform a method of testing an electronic circuit, the method comprising:
-
receiving a signature from a time compactor associated with an electronic circuit; determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor; and storing the list of initial candidate fault locations. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. One or more computer-readable memory or storage devices storing a list of candidate fault locations, the list of candidate fault locations having been produced according to a method comprising:
-
receiving a signature from a time compactor associated with an electronic circuit; and determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor.
-
-
21. A system for testing an electronic circuit comprising:
-
means for receiving a signature from a time compactor associated with an electronic circuit; means for determining a list of initial candidate fault locations using one or more error functions associated with the time compactor, the candidate fault locations corresponding to logic instances in the electronic circuit, the error functions being indicative of scan cells in the electronic circuit that at least partially contribute to the value of one or more failing compactor bits in the signature, the one or more error functions having been determined at least in part by simulating an unloading of error values from the scan cells in the electronic circuit into the time compactor; and means for storing the list of initial candidate fault locations on one or more computer readable media.
-
-
22. A method, comprising:
-
determining one or more error signatures, the one or more error signatures describing the effects of one or more error values captured in one or more scan cells in one or more scan chains of an integrated circuit design on a compactor signature produced by a compactor coupled to the one or more scan chains, the compactor signature comprising a plurality of compactor bits, and the determining the one or more error signatures comprising simulating an unloading of the one or more error values from the one or more scan cells into the compactor; producing an error function for a selected compactor bit from one or more of the determined error signatures, the error function describing the effect of one or more of the scan cells on the value of the selected compactor bit; storing the error function on one or more computer-readable media; receiving a failing signature generated from an implementation of the compactor, the failing signature including a failing value at the selected compactor bit; and determining a list of initial circuit defect candidate locations based at least in part on the error function and using a path-tracing technique. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer to perform a method, the method comprising:
-
determining one or more error signatures, the one or more error signatures describing the effects of one or more error values captured in one or more scan cells in one or more scan chains of an integrated circuit design on a compactor signature produced by a compactor coupled to the one or more scan chains, the compactor signature comprising a plurality of compactor bits, the determining the one or more error signatures comprising simulating an unloading of the one or more error values from the one or more scan cells into the compactor; producing an error function for a selected compactor bit from one or more of the determined error signatures, the error function describing the effect of one or more of the scan cells on the value of the selected compactor bit; storing the error function; receiving a failing signature generated from an implementation of the compactor, the failing signature including a failing value at the selected compactor bit; and determining a list of initial circuit defect candidate locations based at least in part on the error function and using a path-tracing technique. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41)
-
-
42. A method of testing an electronic circuit, the method comprising:
-
using a time compactor to generate a signature from test results stored in a plurality of scan chains in the electronic circuit, the test results being generated after application of a test pattern; identifying scan cells that possibly captured error values caused by one or more faulty logic instances in the electronic circuit as a result of the application of the test pattern using a description of an association between scan cells in the circuit and signature bits in the signature generated by the compactor, the description being determined at least in part by simulating an unloading of a value representing an error captured by one of the scan cells into the time compactor; and storing a list of the scan cells identified. - View Dependent Claims (43, 44, 45)
-
Specification