Compactor independent direct diagnosis of test hardware
First Claim
1. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer system to perform a method, the method comprising diagnosing one or more faulty scan cells in one or more scan chains of an at least partially scan-based circuit-under-test using compressed test responses to chain patterns and compressed responses to scan patterns.
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Accused Products
Abstract
Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
72 Citations
20 Claims
- 1. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer system to perform a method, the method comprising diagnosing one or more faulty scan cells in one or more scan chains of an at least partially scan-based circuit-under-test using compressed test responses to chain patterns and compressed responses to scan patterns.
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10. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer system to perform a method of testing an integrated circuit, the method comprising:
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receiving test responses from testing scan chains of a circuit-under-test using multiple chain patterns, wherein the testing comprises, applying at least one of the chain patterns to the scan chains through a decompressor and a compactor coupled to the scan chains, and applying at least one of the chain patterns to the scan chains while bypassing the decompressor and the compactor; and determining whether a fault exists in the scan chains of the circuit-under-test or in the decompressor or the compactor based at least in part on test responses to the chain patterns applied during the testing. - View Dependent Claims (11, 12, 13)
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14. One or more computer-readable memory or storage devices comprising computer-executable instructions for causing a computer system to perform a method of testing an integrated circuit, the method comprising:
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simulating one or more test patterns being applied to an integrated circuit design having scan chains and a compactor and thereby generating one or more expected compressed test responses, the act of simulating comprising modifying test values of the test patterns so that scan cells of a selected scan chain are loaded with either unknown values or a fixed value, the act of simulating further comprising using a transformation function representative of the compactor to generate the expected compressed test responses; comparing the expected compressed test responses to observed compressed test responses obtained from testing a physical embodiment of the integrated circuit design with the one or more test patterns; and determining a range of suspect scan cells in the selected scan chain based at least in part on the comparison. - View Dependent Claims (15, 16, 17, 18)
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19. One or more computer-readable memory or storage devices storing computer-executable instructions for causing a computer system to perform a method, the method comprising:
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receiving a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test; determining a transformation function performed by the compactor to the test responses captured in the circuit-under-test; and diagnosing scan chain faults in one or more scan chains of the circuit-under-test using a diagnostic procedure that incorporates the transformation function. - View Dependent Claims (20)
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Specification