Multi-processor system receiving input from a pre-fetch buffer

• US 8,281,079 B2
• Filed: 01/13/2004
• Issued: 10/02/2012
• Est. Priority Date: 01/13/2004
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Steely, Simon C. Jr., Tierney, Gregory Edward
• Primary Examiner(s): Campos, Yaima
• Assistant Examiner(s): Dillon, Samuel
• Application Number:
  US10/756,535
• Publication Number:
  US 20050154836A1
• Time in Patent Office: 3,185 Days
• Field of Search: 711/119, 711/124, 711/141, 711/144
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

Claims

1. A multi-processor system that conforms to a cache coherency protocol, the system comprising:

a pre-fetch buffer that retrieves data from at least one of a main memory of the multi-processor system and a cache associated with a processor of the multi-processor system as an uncached fill, such that the cache coherency state of the data remains unaltered; and

a source processor that processes the data from the pre-fetch buffer in response to a source request, the source processor processes the data as a speculative data fill until a coherent signal is received, the coherent signal indicating whether the speculative data fill is coherent, wherein the speculative fill is a copy of the data that has an undetermined coherency state, and the source processor continues to execute program instructions with the speculative data fill,

the source processor having a request engine that sends the source request to obtain at least one data fill from the multi-processor system, the request engine generating a miss address file (MAF) entry associated with the source request, the MAF entry having a field for storing the at least one data fill and a coherent flag that indicates if the coherent signal has been received by the source processor.

2. The system of claim 1, the at least one data fill comprising a coherent data fill, and the source processor returning to a previous state and processing the coherent data fill if it is indicated that the speculative data fill is not a coherent copy of the data.

3. The system of claim 2, further comprising a fill control component that compares the coherent data fill with the speculative data fill, the fill control component providing the coherent data fill to the source processor if the speculative data fill is the same as coherent data fill and providing the coherent signal to the source processor if the speculative data fill is not the same as the coherent data fill.

4. The system of claim 1, the coherent signal indicating a coherent data fill from the at least one data fill.

5. The system of claim 1, the request engine storing a latest data fill received by the source processor in the MAF entry field for storing at least one data fill and changing the state of the coherent flag in response to receipt of the coherent signal by the source processor.