Reconfigurable general purpose processor having time restricted configurations

• US 8,281,108 B2
• Filed: 01/20/2003
• Issued: 10/02/2012
• Est. Priority Date: 01/19/2002
• Status: Expired due to Term

• Current Assignee: Maren Krass, Thomas Richter
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Baumgarte, Volker
• Primary Examiner(s): VICARY, KEITH E
• Application Number:
  US10/501,845
• Publication Number:
  US 20060090062A1
• Time in Patent Office: 3,543 Days
• Field of Search: 712/15, 712/34, 712/55, 714/55
• US Class Current: 712/15
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE.

Claims

1. A method of data processing using a processor comprising a reconfigurable field of data processing cells, the method comprising:

configuring, by the processor, a first subset of the data processing cells, such that the first subset of the data processing cells has a first configuration while one or more other subsets of the data processing cells has, respectively, one or more other configurations;

processing data, by the first subset of the data processing cells, while the first subset of the data processing cells is configured with the first configuration;

monitoring, by the processor, whether a maximum allowed execution runtime of the first configuration is exceeded; and

responsive to determining, in the monitoring step, that the maximum allowed execution runtime of the first configuration is exceeded, removing, by the processor, the first configuration and the one or more other configurations.

2. The method of claim 1, where the maximum allowed execution runtime of the first configuration is determined by the processor to be exceeded conditional upon a lapse of the maximum allowed execution runtime without the first subset of the data processing cells requesting a new configuration.

3. The method of claim 1, wherein the first subset of the data processing cells is adapted to, while the first subset of the data processing cells is configured with the first configuration, request a new configuration of one or more of the first subset of the data processing cells.

4. A method of data processing using a processor comprising a reconfigurable field of data processing cells and a memory arrangement, wherein the memory arrangement stores therein a data vector, the method comprising:

sequentially reading, by the field using a first configuration of the field, a first subset of data elements of the data vector;

monitoring whether a maximum allowed execution runtime of the first configuration is exceeded;

responsive to determining in the monitoring step that the maximum allowed execution runtime is exceeded, removing the first configuration and configuring the field with a second configuration prior to readout of all of the data elements of the data vector, such that a second subset of the data elements of the data vector remains unread in the memory arrangement; and

subsequent to the removing of the first configuration and the configuring of the field with the second configuration, sequentially reading, by the field using the second configuration, one or more data elements of the second subset of the data elements.

5. The method of claim 4, further comprising:

for each of the sequentially read data elements, updating a pointer to point to a different memory location of the memory arrangement than prior to the updating, wherein a beginning of the sequential reading of the one or more data elements of the second subset of the data element is performed based on a position into which the pointer entered while the field was configured with the first configuration.