Apparatus for detecting and recovering from data destruction caused in an unaccessed memory cell by read, and method therefor

• US 8,281,220 B2
• Filed: 01/03/2008
• Issued: 10/02/2012
• Est. Priority Date: 05/16/2007
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kitahara, Jun
• Primary Examiner(s): Bhatia, Ajay
• Assistant Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US11/968,724
• Publication Number:
  US 20080288814A1
• Time in Patent Office: 1,734 Days
• Field of Search: None
• US Class Current: 714/764
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

Read error in a flash memory destroys data that is not requested to be read, and an efficient read disturb check method is therefore needed. In addition, data may be destroyed beyond repair by error correction before a read error check is run. A non-volatile data storage apparatus including a plurality of memory cells and a memory controller, in which the memory controller is configured to: count how many times data read processing has been executed in memory cells within the management area; read, when the data read processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells within the first management area; decode the read error correction code; and write the data corrected by decoding the error correction code in other management areas than the first management area.

Claims

1. A non-volatile data storage apparatus, comprising:

a plurality of memory chips; and

a memory controller coupled to the plurality of memory chips

wherein each of the memory chips includes a plurality of management areas,

wherein the memory controller is configured to;

write, in the plurality of memory chips, data and an error correction code calculated from the data;

count the number of data read processing for each of the management areas;

read, when the number of data read processing that is counted for a first management area of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the first management area;

decode the error correction code read from the first management area; and

write the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the first threshold is decreased with increasing an erase count in the first management area.

3. The non-volatile data storage apparatus according to claim 1, wherein the memory controller is further configured to use, when the data read processing count that is counted for the first management area exceeds a seventh threshold, an eighth threshold in place of the first threshold, the eighth threshold being smaller than the first threshold.

4. The non-volatile data storage apparatus according to claim 1,

wherein the plurality of memory chips include memory chips of a NAND flash memory, and

wherein each of the management areas includes the field effect transistor in a plurality of numbers, the plurality of the field effect transistors being connected in series and individually belonging to different pages, and the field effect transistor in a plurality of numbers included in each of the pages.

2. A non-volatile data storage apparatus, comprising:

a plurality of memory cells; and

a memory controller coupled to the plurality of memory cells, for controlling data write and read in the plurality of memory cells,

wherein each of the memory cells includes a field effect transistor having a floating gate,

wherein each of the memory cells is included in one of a plurality of management areas,

wherein the management areas each include at least two of the memory cells, and

wherein the memory controller is configured to;

write, in the plurality of memory cells, data and an error correction code calculated from the data;

count, for each of the management areas, how many times data read processing has been executed in the memory cells within the management area;

read, when the data read processing count that is counted for a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the memory cells within the first management area;

decode the error correction code read from the first management area; and

write, when a count of errors included in the read data exceeds a second threshold, the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the memory controller is further configured to;

count how many times the processing of writing corrected data in other management areas than the first management area has been executed as a result of the error count of data read out of the first management area exceeding the second threshold; and

use, when the execution count of the processing of writing corrected data in other management areas than the first management area exceeds a fifth threshold, a sixth threshold in place of the first threshold, the sixth threshold being smaller than the first threshold.

5. A non-volatile data storage apparatus, comprising:

a plurality of memory cells; and

a memory controller coupled to the plurality of memory cells, for controlling data write and read in the plurality of memory cells,

wherein each of the memory cells includes a field effect transistor having a floating gate,

wherein each of the memory cells is included in one of a plurality of management areas,

wherein the management areas each include at least two of the memory cells, and

wherein the memory controller is configured to;

write, in the plurality of memory cells, data and an error correction code calculated from the data;

count, for each of the management areas, how many times data read processing has been executed in the memory cells within the management area;

read, when the data read processing count that is counted for a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the memory cells within the first management area;

decode the error correction code read from the first management area; and

write, when a count of errors included in the read data exceeds a second threshold, the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the non-volatile data storage apparatus is coupled to a host device for sending a data write request and a data read request to the non-volatile data storage apparatus, and

wherein the memory controller is further configured to send, when the data read out of the memory cells in the first management area includes an error that cannot be corrected by decoding the error correction code, information indicating an address assigned to an area in which the error that cannot be corrected by decoding of the error correction code has been written to the host device.

6. A storage system, comprising:

a plurality of non-volatile data storage apparatuses; and

a storage controller for sending a data write request and a data read request to the plurality of non-volatile data storage apparatuses,

wherein the storage controller writes, in at least one of the plurality of non-volatile data storage apparatuses, data that provides redundancy to data written in at least one of the non-volatile data storage apparatuses, which exclude the at least one non-volatile data storage apparatus holding the redundant data,

wherein each of the non-volatile data storage apparatuses has a plurality of memory cells and a memory controller coupled to the plurality of memory cells, for controlling data write and read in the memory cells,

wherein each of the memory cells includes a field effect transistor having a floating gate,

wherein each of the memory cells is included in one of a plurality of management areas,

wherein the management areas each include at least two of the memory cells,

wherein the memory controller is configured to;

write, in the plurality of memory cells, data requested by the storage controller to be written and an error correction code calculated from the data;

count, for each of the management areas, how many times data read processing has been executed in the memory cells within the management area;

read, when the data read processing count that is counted for a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the memory cells within the first management area;

decode the read error correction code;

write, when a count of errors included in the read data exceeds a second threshold, the data corrected by decoding the error correction code in other management areas than the first management area; and

send, when the read data includes an error that cannot be corrected by decoding the error correction code, information indicating an address assigned to an area that holds the data including the error that cannot be corrected by decoding of the error correction code, and

wherein the storage controller is configured to;

send, to the plurality of non-volatile data storage apparatuses, a data read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code and an area that holds data for providing redundancy to the data including the error that cannot be corrected by decoding of the error correction code;

restore the data including the error that cannot be corrected by decoding of the error correction code from the data read in response to the read request; and

send, to the plurality of non-volatile data storage apparatuses, a request to write the restored data and data that provides redundancy to the restored data.

7. The storage system according to claim 6, further comprising:

a control device which is coupled to the plurality of non-volatile data storage apparatuses and to the storage controller,

wherein the memory controller is further configured to send, when the read data includes an error that cannot be corrected by decoding the error correction code, to the control device, information indicating an address assigned to an area that holds the data including the error that cannot be corrected by decoding of the error correction code,

wherein the control device is configured to send, to the storage controller, a read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code, and

wherein the storage controller is further configured to send, in response to the read request received from the control device, to the plurality of non-volatile data storage apparatuses, a data read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code and an area that holds data for providing redundancy to the data including the error that cannot be corrected by decoding of the error correction code.

8. The storage system according to claim 6, wherein the data that provides redundancy to the data written in at least one of the non-volatile data storage apparatuses is one of the same data as the data written in the at least one of the non-volatile data storage apparatuses and parity calculated from the data written in the at least one of the non-volatile data storage apparatuses.

9. A method of controlling a storage system including a non-volatile data storage apparatus that has a plurality of memory chips and a memory controller which is coupled to the plurality of memory chips, each of the memory chips includes a plurality of management areas, the method comprising the steps of:

writing, by the memory controller, data and an error correction code, which is calculated from the data, in the plurality of memory chips;

counting, by the memory controller, the number of data read processing for each of the management areas

reading, by the memory controller, when the number of data read processing is counted for a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the first management area;

decoding, by the memory controller, the error correction code read from the first management area; and

writing, by the memory controller, the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the first threshold is decreased with increasing an erase count in the first management area.

11. The storage system control method according to claim 9, wherein, when the data read processing count that is counted for the first management area exceeds a seventh threshold, the memory controller uses an eighth threshold in place of the first threshold, the eighth threshold being smaller than the first threshold.

12. The storage system control method according to claim 9,

wherein the plurality of memory chips include memory cells of a NAND flash memory, and

wherein each of the management areas includes the field effect transistor in a plurality of numbers, the plurality of the field effect transistors being connected in series and individually belonging to different pages, and the field effect transistor in a plurality of numbers included in each of the pages.

10. A method of controlling a storage system including a non-volatile data storage apparatus that has a plurality of memory cells and a memory controller which is coupled to the plurality of memory cells, for controlling data write and read in the memory cells, each of the memory cells being a field effect transistor with a floating gate and included in one of a plurality of management areas, the management areas each including at least two of the memory cells, the method comprising the steps of:

writing, by the memory controller, data and an error correction code, which is calculated from the data, in the plurality of memory cells;

counting, by the memory controller, for each of the management areas, how many times data read processing has been executed in the memory cells within the management area;

reading, by the memory controller, when the data read processing count of a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the memory cells within the first management area;

decoding, by the memory controller, the read error correction code;

writing, by the memory controller, when a count of errors included in the read data exceeds a second threshold, the data corrected by decoding the error correction code in other management areas than the first management area; and

counting, by the memory controller, how many times the processing of writing corrected data in other management areas than the first management area has been executed as a result of the error count of data read out of the first management area exceeding the second threshold,

wherein, when the execution count of the processing of writing corrected data in other management areas than the first management area exceeds a fifth threshold, the memory controller uses a sixth threshold in place of the first threshold, the sixth threshold being smaller than the first threshold.

13. A method of controlling a storage system including a non-volatile data storage apparatus that has a plurality of memory cells and a memory controller which is coupled to the plurality of memory cells, for controlling data write and read in the memory cells, each of the memory cells being a field effect transistor with a floating gate and included in one of a plurality of management areas, the management areas each including at least two of the memory cells, the method comprising the steps of:

writing, by the memory controller, data and an error correction code, which is calculated from the data, in the plurality of memory cells;

counting, by the memory controller, for each of the management areas, how many times data read processing has been executed in the memory cells within the management area;

reading, by the memory controller, when the data read processing count of a first management area, which is one of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the memory cells within the first management area;

decoding, by the memory controller, the read error correction code; and

writing, by the memory controller, when a count of errors included in the read data exceeds a second threshold, the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the non-volatile data storage apparatus is coupled to a host device for sending a data write request and a data read request to the non-volatile data storage apparatus, and

wherein the method further comprises the step of sending, by the memory controller, when the data read out of the memory cells in the first management area includes an error that cannot be corrected by decoding the error correction code, information indicating an address assigned to an area in which the error that cannot be corrected by decoding of the error correction code has been written to the host device.

14. The storage system control method according to claim 13, wherein the storage system includes the non-volatile data storage apparatuses in a plurality of numbers,

wherein the host device includes a storage controller for sending a data write request and a data read request to the plurality of non-volatile data storage apparatuses,

wherein the storage controller writes, in at least one of the plurality of non-volatile data storage apparatuses, data that provides redundancy to data written in at least one of the non-volatile data storage apparatuses, which exclude the at least one non-volatile data storage apparatus holding the redundant data,

wherein the step of writing, by the memory controller, data and an error correction code, which is calculated from the data, in the plurality of memory cells is executed in response to the data write request sent from the storage controller, and

wherein the method further comprises the steps of:

sending, by the storage controller, to the plurality of non-volatile data storage apparatuses, a data read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code and an area that holds data for providing redundancy to the data including the error that cannot be corrected by decoding of the error correction code;

restoring, by the storage controller, the data including the error that cannot be corrected by decoding of the error correction code from the data read in response to the read request; and

sending, by the storage controller, to the plurality of non-volatile data storage apparatuses, a request to write the restored data and data that provides redundancy to the restored data.

15. The storage system control method according to claim 14, wherein the host device further includes a control device coupled to the plurality of non-volatile data storage apparatuses and to the storage controller,

wherein the method further comprises the steps of:

receiving, by the control device, information indicating an address assigned to the area that holds the data including the error that cannot be corrected by decoding of the error correction code; and

sending, by the control device, to the storage controller, a read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code, and

wherein the step of sending, by the storage controller, a data read request to the plurality of non-volatile data storage apparatuses is executed in response to the read request received from the control device.

16. The storage system control method according to claim 14, wherein the data that provides redundancy to the data written in at least one of the non-volatile data storage apparatuses is one of the same data as the data written in the at least one of the non-volatile data storage apparatuses and parity calculated from the data written in the at least one of the non-volatile data storage apparatuses.

17. A storage system comprising:

a plurality of non-volatile data storage apparatus; and

a storage controller coupled to the plurality of non-volatile data storage apparatus,

wherein each non-volatile data storage apparatus comprises;

a plurality of memory chips, and

a memory controller coupled to the plurality of memory chips,

wherein each of the memory chips includes a plurality of management areas,

wherein the memory controller is configured to;

write, in the plurality of memory chips, data and an error correction code calculated from the data;

count the number of data read processing for each of the management areas;

read, when the number of data read processing that is counted for a first management area of the plurality of management areas, exceeds a first threshold, the data and the error correction code that are stored in the first management area;

decode the error correction code read from the first management area; and

write the data corrected by decoding the error correction code in other management areas than the first management area,

wherein the first threshold is decreased with increasing an erase count in the first management area.

18. The storage system according to claim 17, wherein the storage controller sends a data write request and a data read request to the plurality of non-volatile data storage apparatus,

wherein the storage controller writes, in at least one of the plurality of non-volatile data storage apparatuses, data that provides redundancy to data written in at least one of the plurality of non-volatile data storage apparatus, which exclude the at least one of the plurality of non-volatile data storage apparatus holding the redundant data,

wherein the memory controller is further configured to:

send, when the read data includes an error that cannot be corrected by decoding the error correction code, information indicating an address assigned to an area that holds the data including the error that cannot be corrected by decoding of the error correction code, and

wherein the storage controller is configured to;

send, to the plurality of non-volatile data storage apparatuses, a data read request for the area that holds the data including the error that cannot be corrected by decoding of the error correction code and an area that holds data for providing redundancy to the data including the error that cannot be corrected by decoding of the error correction code,

restore the data including the error that cannot be corrected by decoding of the error correction code from the data read in response to the read request, and

send, to the plurality of non-volatile data storage apparatuses, a request to write the restored data and data that provides redundancy to the restored data.