Method and device for information block coding and synchronization detecting

• US 8,281,228 B2
• Filed: 03/30/2011
• Issued: 10/02/2012
• Est. Priority Date: 05/26/2007
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Geng, Dongyu, Feng, Dongning, Leung, Raymond W. K., Effenberger, Frank
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US13/075,931
• Publication Number:
  US 20110173516A1
• Time in Patent Office: 552 Days
• Field of Search: 714/755, 714/789, 714/798
• US Class Current: 714/798
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/333 Synchronisation on a multi-bit block basis, e.g. frame synchronisation
• CPC Class Codes: H03M 13/6522 Intended application, e.g. transmission or communication standard
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Claims

1. A method for check information block coding in 10 gigabit per second Ethernet passive optical network (EPON), comprising:

adding a synchronization header to each of a plurality of data information blocks, wherein the synchronization header comprises a bit indicating an information type of the corresponding data information block;

performing a forward error correction (FEC) coding on a predetermined number of the data information blocks and the bits in the synchronization headers associated with the data information blocks to generate M continuous check information blocks following the predetermined number of the data information blocks;

adding a synchronization character to each of the M continuous check information blocks according to a synchronization character sequence {T_j}, wherein one check information block with one synchronization character comprises 66 bits, wherein the synchronization character is used for synchronization of the check information blocks and the synchronization character is “

00”

or “

11”

, wherein the synchronization character added to a j^th check information block P_j is T_j, and the synchronization character sequence {T_j} satisfies the following conditions;

2. The method according to claim 1, wherein

M=4;

and

the synchronization character sequence {T_j} is {A,B,B,A} or {B,A,A,B}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.

3. The method according to claim 1, wherein

M=5;

and

the synchronization character sequence {Tj} is one of the following sequences;

{A,A,B,A,B};

{A,A,B,B,A};

{A,B,A,A,B};

{A,B,A,B,B};

{A,B,B,A,A};

{A,B,B,A,B};

{A,B,B,B,A};

{B,A,A,A,B};

{B,A,A,B,A};

{B,A,A,B,B};

{B,A,B,A,A};

{B,A,B,B,A};

{B,B,A,A,B};

{B,B,A,B,A}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.

4. The method according to claim 1, wherein

M=6;

and

the synchronization character sequence {Tj} is one of the following sequences;

{A,A,B,B,A,B};

{A,B,A,A,B,B};

{A,B,A,B,B,A};

{A,B,B,A,B,A};

{B,A,A,B,A,B};

{B,A,B,A,A,B};

{B,A,B,B,A,A};

{B,B,A,A,B,A}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.

5. A device for coding check information blocks of forward error correction (FEC) code words in a 10 gigabit per second Ethernet passive optical network (EPON), comprising:

a sequence storage module, adapted to store a synchronization character sequence {T_j}, wherein the {T_j} satisfy the following conditions;

6. The device according to claim 5, wherein

M=4;

and

the synchronization character sequence {T_j} is {A,B,B,A} or {B,A,A,B}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.

7. The device according to claim 5, wherein

M=5;

and

the synchronization character sequence {Tj} is one of the following sequences;

{A,A,B,A,B};

{A,A,B,B,A};

{A,B,A,A,B};

{A,B,A,B,B};

{A,B,B,A,A};

{A,B,B,A,B};

{A,B,B,B,A};

{B,A,A,A,B};

{B,A,A,B,A};

{B,A,A,B,B};

{B,A,B,A,A};

{B,A,B,B,A};

{B,B,A,A,B};

{B,B,A,B,A}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.

8. The device according to claim 5, wherein

M=6;

and

the synchronization character sequence {Tj} is one of the following sequences;

{A,A,B,B,A,B};

{A,B,A,A,B,B};

{A,B,A,B,B,A};

{A,B,B,A,B,A};

{B,A,A,B,A,B};

{B,A,B,A,A,B};

{B,A,B,B,A,A};

{B,B,A,A,B,A}, wherein A is different from B;

wherein A is one of the “

00”

or “

11” and

B is the other.