Method and apparatus for versatile controllability and observability in prototype system
First Claim
1. A prototyping system for verifying and debugging an integrated circuit design under verification (DUV) comprising:
- a host workstation comprising a processor and a first memory, the host workstation configured to provide a plurality of configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the plurality of FPGA images is downloaded to a respective FPGA device, of a of FPGA devices, and each of the plurality of FPGA images contains a portion of the DUV, and a respective verification module, of a plurality of verification modules, wherein each of the plurality of verification modules is associated with a respective FPGA device; and
an interface configured to provide timing and control information to each of the plurality of verification modules based on the runtime control information received from the host workstation, the interface comprising a controller and a second memory, the second memory being configured to store probed signal values associated with a first portion of the DUV received from a first verification module, of the of verification modules, and the controller being configured to process the probed signal values,wherein the first verification module is coupled with the interface and configured to control and probe the signal values of the first portion of the DUV in response to the timing and control information received from the interface, wherein the first portion of the DUV corresponds to a first FPGA device of the plurality of FPGA devices.
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Accused Products
Abstract
Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.
18 Citations
17 Claims
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1. A prototyping system for verifying and debugging an integrated circuit design under verification (DUV) comprising:
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a host workstation comprising a processor and a first memory, the host workstation configured to provide a plurality of configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the plurality of FPGA images is downloaded to a respective FPGA device, of a of FPGA devices, and each of the plurality of FPGA images contains a portion of the DUV, and a respective verification module, of a plurality of verification modules, wherein each of the plurality of verification modules is associated with a respective FPGA device; and an interface configured to provide timing and control information to each of the plurality of verification modules based on the runtime control information received from the host workstation, the interface comprising a controller and a second memory, the second memory being configured to store probed signal values associated with a first portion of the DUV received from a first verification module, of the of verification modules, and the controller being configured to process the probed signal values, wherein the first verification module is coupled with the interface and configured to control and probe the signal values of the first portion of the DUV in response to the timing and control information received from the interface, wherein the first portion of the DUV corresponds to a first FPGA device of the plurality of FPGA devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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receiving, at an interface, from a host workstation, a plurality of configured Field Programmable Gate Array FPGA images and runtime control information, wherein each of the plurality of FPGA images contains a respective portion of an integrated circuit design under verification (DUV), and a respective verification module, of a plurality of verification modules, wherein each of the plurality of verification modules is associated with a respective FPGA device of a plurality of FPGA devices, and each of the FPGA images is downloaded to a respective FPGA device, of a plurality of FPGA devices; sending, by the interface, each of the received plurality of configured FPGA images to each of the respective FPGA devices; sending, by the interface, timing and control information to each of the respective verification modules, of the plurality of verification modules, based on the runtime control information received from the host workstation; controlling, by each of the respective verification modules, the respective portion of the DUV in each of the respective FPGA devices in response to the timing and control information received from the interface; receiving, by the interface, from a first verification module of the plurality of verification modules, probed signal values associated with a first portion of the DUV; and processing and storing in a memory within the interface, by a controller in the interface, at least a portion of the probed signal values received from the first verification module. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification