Method of making a semiconductor chip assembly with a bump/base heat spreader and a dual-angle cavity in the bump

• US 8,283,211 B2
• Filed: 11/22/2010
• Issued: 10/09/2012
• Est. Priority Date: 03/25/2008
• Status: Expired due to Fees

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Lin, Charles W. C., Wang, Chia-Chung
• Primary Examiner(s): Wagner, Jenny L
• Assistant Examiner(s): BOYLE, ABBIGALE A
• Application Number:
  US12/951,066
• Publication Number:
  US 20110065241A1
• Time in Patent Office: 687 Days
• Field of Search: 438106-127, 438/26, 438/29, 257/99, 257/712, 257/676
• US Class Current: 438/122
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32013 the layer connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 Epoxy resin
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/642 characterized by the shape

Abstract

A method of making a semiconductor chip assembly includes providing a bump and a ledge, wherein the bump includes first, second and third bent corners that shape a cavity, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the ledge, providing a heat spreader that includes the bump, then mounting a semiconductor device on the bump within the cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Claims

1. A method of making a semiconductor chip assembly, comprising:

providing a bump, a ledge, an adhesive and a substrate, wherein

the bump includes first, second and third bent corners, first and second sidewalls and a floor, the second bent corner is between the first and third bent corners, the first sidewall extends between the first and second bent corners, the second sidewall extends between the second and third bent corners and the floor is adjacent to the third bent corner, the bump defines a cavity that faces in a first vertical direction, has an entrance at the ledge, is shaped by the first, second and third bent corners, the first and second sidewalls and the floor and has a first angle relative to the floor at the first sidewall and a second angle relative to the floor at the second sidewall and the bump is adjacent to and integral with the ledge at the first bent corner, is spaced from the ledge at the second and third bent corners, extends vertically from the ledge in a second vertical direction opposite the first vertical direction, extends into an opening in the adhesive and is aligned with an aperture in the substrate,

the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions,

the adhesive is mounted on the ledge, is sandwiched between the ledge and the substrate and is non-solidified, and

the substrate is mounted on the adhesive, wherein the substrate includes a conductive layer and a dielectric layer and the dielectric layer is sandwiched between the conductive layer and the adhesive;

then

flowing the adhesive in the second vertical direction into a gap located in the aperture between the bump and the conductive layer;

solidifying the adhesive;

then

providing a conductive trace that includes a pad, a terminal, a plated through-hole, a selected portion of the ledge that is adjacent to the plated through-hole and spaced from the bump and a selected portion of the conductive layer that is adjacent to the plated through-hole and spaced from the bump, wherein the plated through-hole is in an electrically conductive path between the pad and the terminal;

providing a heat spreader that includes the bump, a base and a flange, wherein the bump is adjacent to the flange at the first bent corner and is spaced from the flange at the second and third bent corners, is adjacent to the base at the third bent corner and the floor and is spaced from the base at the first and second bent corners and extends vertically from the base in the first vertical direction, the base covers the bump in the second vertical direction, extends laterally from the bump and includes a selected portion of the conductive layer that is spaced from the conductive trace and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device is located within the cavity, extends beyond the first bent corner in the second vertical direction but not the first vertical direction, extends beyond the second bent corner in the first and second vertical directions and extends beyond the third bent corner in the first vertical direction but not the second vertical direction and the bump provides a recessed die paddle and a reflector for the semiconductor device;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

2. The method of claim 1, wherein providing the bump includes mechanically stamping a metal plate, thereby forming the bump in the metal plate and the first, second and third bent corners and the cavity in the bump, wherein the bump is a stamped portion of the metal plate, the ledge is an unstamped portion of the metal plate and the first, second and third bent corners are bent portions of the metal plate.

3. The method of claim 1, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

4. The method of claim 1, wherein flowing the adhesive includes filling the gap with the adhesive.

5. The method of claim 1, wherein providing the pad and the flange includes removing selected portions of the ledge using an etch mask that defines the pad and the flange after forming the plated through-hole.

6. The method of claim 1, wherein providing the pad, the flange and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the bump, the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a first plated layer on the bump and the ledge that covers the bump in the first vertical direction and the plated through-hole in the hole;

then

forming an etch mask on the first plated layer that defines the pad and the flange;

etching the ledge and the first plated layer in a pattern defined by the etch mask; and

then removing the etch mask.

7. The method of claim 1, wherein providing the base and the terminal includes removing selected portions of the conductive layer using an etch mask that defines the base and the terminal after forming the plated through-hole.

8. The method of claim 1, wherein providing the base and the terminal includes:

grinding the bump, the adhesive and the conductive layer such that the bump, the adhesive and the conductive layer are laterally aligned with one another at a lateral surface that faces in the second vertical direction; and

then

removing selected portions of the conductive layer using an etch mask that defines the base and the terminal.

9. The method of claim 1, wherein providing the base, the terminal and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a second plated layer on the bump, the adhesive and the conductive layer that covers the bump in the second vertical direction and the plated through-hole in the hole;

then

forming an etch mask on the second plated layer that defines the base and the terminal;

etching the conductive layer and the second plated layer in a pattern defined by the etch mask; and

then

removing the etch mask.

10. The method of claim 1, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.

11. A method of making a semiconductor chip assembly, comprising:

providing a bump and a ledge, wherein the bump includes first, second and third bent corners, first and second sidewalls and a floor, the second bent corner is between the first and third bent corners, the first sidewall extends between the first and second bent corners, the second sidewall extends between the second and third bent corners and the floor is adjacent to the third bent corner, the bump defines a cavity that faces in a first vertical direction, has an entrance at the ledge, is shaped by the first, second and third bent corners, the first and second sidewalls and the floor and has a first angle relative to the floor at the first sidewall and a second angle relative to the floor at the second sidewall, the bump is adjacent to and integral with the ledge at the first bent corner, is spaced from the ledge at the second and third bent corners and extends vertically from the ledge in a second vertical direction opposite the first vertical direction and the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions;

providing an adhesive, wherein an opening extends through the adhesive;

providing a substrate that includes a conductive layer and a dielectric layer, wherein an aperture extends through the substrate;

mounting the adhesive on the ledge, including inserting the bump into the opening, wherein the bump extends through the opening;

mounting the substrate on the adhesive, including inserting the bump into the aperture, wherein the bump extends into the aperture, the adhesive is sandwiched between the ledge and the dielectric layer and is non-solidified and the dielectric layer is sandwiched between the conductive layer and the adhesive;

then

applying heat to melt the adhesive;

moving the ledge and the substrate towards one another, thereby moving the bump in the second vertical direction in the aperture and applying pressure to the molten adhesive between the ledge and the substrate, wherein the pressure forces the molten adhesive to flow in the second vertical direction into a gap located in the aperture between the bump and the substrate;

applying heat to solidify the molten adhesive, thereby mechanically attaching the bump and the ledge to the substrate;

then

providing a plated through-hole that extends through the ledge, the adhesive, the dielectric layer and the conductive layer;

then

providing a pad, a terminal, a base and a flange;

providing a conductive trace that includes the pad, the terminal, the plated through-hole, a selected portion of the ledge that is adjacent to the plated through-hole and spaced from the bump and a selected portion of the conductive layer that is adjacent to the plated through-hole and spaced from the bump, wherein the plated through-hole is in an electrically conductive path between the pad and the terminal;

providing a heat spreader that includes the bump, the base and the flange, wherein the bump is adjacent to the flange at the first bent corner and is spaced from the flange at the second and third bent corners, is adjacent to the base at the third bent corner and the floor and is spaced from the base at the first and second bent corners and extends vertically from the base in the first vertical direction, the base covers the bump in the second vertical direction, extends laterally from the bump in the lateral directions and includes a selected portion of the conductive layer that is spaced from the conductive trace and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device is located within the cavity, extends beyond the first bent corner in the second vertical direction but not the first vertical direction, extends beyond the second bent corner in the first and second vertical directions and extends beyond the third bent corner in the first vertical direction but not the second vertical direction and the bump provides a recessed die paddle and a reflector for the semiconductor device;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

12. The method of claim 11, wherein providing the bump includes mechanically stamping a metal plate, thereby forming the bump in the metal plate and the first, second and third bent corners and the cavity in the bump, wherein the bump is a stamped portion of the metal plate, the ledge is an unstamped portion of the metal plate and the first, second and third bent corners are bent portions of the metal plate.

13. The method of claim 11, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

14. The method of claim 11, wherein providing the base, the flange, the pad, the terminal and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the bump, the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a first plated layer on the bump and the ledge that covers the bump in the first vertical direction, a second plated layer on the bump, the adhesive and the conductive layer that covers the bump, the adhesive and the conductive layer in the second vertical direction and the plated through-hole in the hole;

then

forming a first etch mask on the first plated layer that defines the pad and the flange;

etching the ledge and the first plated layer in a pattern defined by the first etch mask,

thereby exposing the adhesive in the first vertical direction without exposing the dielectric layer in the first vertical direction;

forming a second etch mask on the second plated layer that defines the base and the terminal;

etching the conductive layer and the second plated layer in a pattern defined by the second etch mask, thereby exposing the dielectric layer in the second vertical direction without

exposing the adhesive in the second vertical direction; and

removing the etch masks.

15. The method of claim 11, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.