Memory device

• US 8,283,662 B2
• Filed: 11/15/2010
• Issued: 10/09/2012
• Est. Priority Date: 11/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US12/946,095
• Publication Number:
  US 20110114946A1
• Time in Patent Office: 694 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/005 with combined beam-and individual cell access
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A memory device without additional logic circuits, including a memory cell which cannot be accessed by a third party and which is always accessible when needed. One embodiment is a memory device including a first memory cell and a second memory cell, and the second memory cell includes a second transistor having a second channel formed of an oxide semiconductor film. Data is read from the second memory cell when the second transistor is being irradiated with ultraviolet rays.

Claims

1. A memory device comprising:

a first memory cell; and

a second memory cell,

the first memory cell comprising a first transistor and a first memory element,

the first transistor comprising a first channel, a first gate electrode, and a first source and drain electrodes,

wherein the first gate electrode is part of a first word line or is electrically connected to the first word line; and

wherein one of the first source and drain electrodes is part of a first bit line or is electrically connected to the first bit line and the other is electrically connected to the first memory element,

the second memory cell comprising a second transistor and a second memory element,

the second transistor comprising a second channel, a second gate electrode, and a second source and drain electrodes,

wherein the second gate electrode is part of a second word line or is electrically connected to the second word line;

wherein the second channel is formed of an oxide semiconductor film; and

wherein one of the second source and drain electrodes is part of a second bit line or is electrically connected to the second bit line and the other is electrically connected to the second memory element,

wherein a threshold voltage (V₂₁) of the second transistor before ultraviolet ray irradiation is higher than a threshold voltage (V₁) of the first transistor;

wherein a threshold voltage (V₂₂) of the second transistor at the time of ultraviolet ray irradiation is lower than the voltage V₂₁;

wherein a threshold voltage (V₂₃) of the second transistor after ultraviolet ray irradiation is lower than the voltage V₂₁ and higher than the voltage V₂₂ and the voltage V₁;

wherein data stored in the second memory element is read when a voltage (V_G) is applied to the second gate electrode of the second transistor which is being irradiated with ultraviolet rays so that the second transistor is turned on; and

wherein V₁≦

V_G (the voltage V_G is equal to or higher than the voltage V₁), and V₂₂≦

V_G<

V₂₃<

V₂₁ (the voltage V_G is equal to or higher than the voltage V₂₂) are satisfied.

2. The memory device according to claim 1, wherein data stored in the first memory element is read by applying the voltage V_G to the first gate electrode to turn on the first transistor.

3. The memory device according to claim 1, wherein the first channel is formed of silicon.

4. The memory device according to claim 1, further comprising a writing circuit, an analog switch, and a third transistor,

the third transistor comprising a third channel, a third gate electrode, and a third source and drain electrodes,

the third channel comprising an oxide semiconductor film,

wherein an output of the writing circuit is input to the analog switch;

wherein an output of the analog switch is input to one of the second source and the drain electrodes of the second transistor;

wherein a writing enable signal is input to one of the third source and drain electrodes, and the other of the third source and drain electrodes is connected to a first control terminal of the analog switch;

wherein an inverted signal of the writing enable signal is input to a second control terminal of the analog switch;

wherein a threshold voltage of the third transistor before ultraviolet ray irradiation is V₃₁;

wherein a threshold voltage of the third transistor at the time of ultraviolet ray irradiation is V₃₂;

wherein a threshold voltage of the third transistor after ultraviolet ray irradiation is V₃₃;

wherein data is written to the second memory element in the following manner;

a voltage (V_A) is applied to the third gate electrode which is being irradiated with ultraviolet rays so that the third transistor is turned on, the writing enable signal is input to the first control terminal, the output of the writing circuit is input to one of the second source and drain electrodes, and a voltage (V_W) is applied to the second gate electrode so that the second transistor is turned on; and

wherein V₃₂≦

V_A<

V₃₃<

V₃₁ (the voltage V_A is equal to or higher than the voltage V₃₂), and V₂₃<

V₂₁<

V_W are satisfied.

5. A memory device comprising:

a first memory cell comprising a first transistor and a first memory element;

a second memory cell comprising a second transistor and a second memory element; and

a third transistor,

the first transistor comprising a first channel, a first gate electrode, and a first source and drain electrodes,

wherein the first gate electrode is part of a first word line or is electrically connected to the first word line; and

wherein one of the first source and drain electrodes is part of a first bit line or is electrically connected to the first bit line and the other is electrically connected to the first memory element,

the second transistor comprising a second channel, a second gate electrode, and a second source and drain electrodes,

wherein the second gate electrode is part of a second word line or is electrically connected to the second word line; and

wherein one of the second source and drain electrodes is part of a second bit line or is electrically connected to the second bit line and the other is electrically connected to the second memory element,

the third transistor comprising a third channel, a third gate electrode, and a third source and drain electrodes,

wherein the third channel is formed of an oxide semiconductor film; and

wherein one of the third source and drain electrodes is electrically connected to the second word line and a selection signal to turn on the second transistor is input to the other of the third source and drain electrodes,

wherein a threshold voltage of the third transistor before ultraviolet ray irradiation is V₃₁;

wherein a threshold voltage of the third transistor at the time of ultraviolet ray irradiation is V₃₂;

wherein a threshold voltage of the third transistor after ultraviolet ray irradiation is V₃₃;

wherein data is written to and read from the second memory element in the following manner;

a voltage (V_G) is applied to the third gate electrode which is being irradiated with ultraviolet rays so that the third transistor is turned on, and the selection signal is input to the second gate electrode so that the second transistor is turned on; and

wherein V₃₂≦

V_G<

V₃₃<

V₃₁ (the voltage V_G is equal to or higher than the voltage V₃₂) is satisfied.

6. The memory device according to claim 5, further comprising a decoder, a level shifter, and a buffer,

wherein one of the third source and drain electrodes is electrically connected to the second word line through the level shifter and the buffer;

and

wherein the selection signal is input from the decoder to the other of the third source and drain electrodes.

7. The memory device according to claim 5, further comprising a decoder, a level shifter, a buffer, and an address line,

wherein one of the third source and drain electrodes is electrically connected to the second word line through the decoder, the level shifter, and the buffer;

and

wherein the selection signal is input from the address line to the other of the third source and drain electrodes.

8. A memory device comprising:

a first memory cell comprising a first transistor and a first memory element;

a second memory cell comprising a second transistor and a second memory element;

a third transistor; and

a fourth transistor,

the first transistor comprising a first channel, a first gate electrode, and a first source and drain electrodes,

wherein the first gate electrode is part of a first word line or is electrically connected to the first word line; and

wherein one of the first source and drain electrodes is part of a first bit line or is electrically connected to the first bit line and the other is electrically connected to the first memory element,

the second transistor comprising a second channel, a second gate electrode, and a second source and drain electrodes,

wherein the second gate electrode is part of a second word line or is electrically connected to the second word line; and

wherein one of the second source and drain electrodes is part of a second bit line or is electrically connected to the second bit line and the other is electrically connected to the second memory element,

the third transistor comprising a third channel, a third gate electrode, and a third source and drain electrodes,

wherein one of the third source and drain electrodes is electrically connected to the second word line and a selection signal to turn on the second transistor is input to the other of the third source and drain electrodes,

the fourth transistor comprising a fourth channel, a fourth gate electrode, and a fourth source and drain electrodes,

wherein the fourth channel is formed of an oxide semiconductor film; and

wherein one of the fourth source and drain electrodes is electrically connected to the third gate electrode and a selection signal to turn on the third transistor is input to the other of the fourth source and drain electrodes,

wherein a threshold voltage of the fourth transistor before ultraviolet ray irradiation is V₃₁;

wherein a threshold voltage of the fourth transistor at the time of ultraviolet ray irradiation is V₃₂;

wherein a threshold voltage of the fourth transistor after ultraviolet ray irradiation is V₃₃;

wherein data is written to and read from the second memory element in the following manner;

a voltage (V_G) is applied to the fourth gate electrode which is being irradiated with ultraviolet rays so that the fourth transistor is turned on and thus the third transistor is turned on, and a selection signal to turn on the second transistor is input to the second gate electrode so that the second transistor is turned on; and

wherein V₃₂≦

V_G<

V₃₃<

V₃₁ (the voltage V_G is equal to or higher than the voltage V₃₂) is satisfied.

9. A memory device comprising:

a first memory cell; and

a second memory cell,

the first memory cell comprising a first transistor and a first memory element,

the first transistor comprising a first channel, a first gate electrode, and a first source and drain electrodes;

wherein the first channel is formed of silicon; and

wherein one of the first source and drain electrodes is electrically connected to the first memory element,

the second memory cell comprising a second transistor and a second memory element,

the second transistor comprising a second channel, a second gate electrode, and a second source and drain electrodes,

wherein the second channel is formed of an oxide semiconductor film; and

wherein one of the second source and drain electrodes is electrically connected to the second memory element,

wherein the first memory cell and the second memory cell are formed over a same substrate.