MOS device with low injection diode

• US 8,283,723 B2
• Filed: 12/21/2007
• Issued: 10/09/2012
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Pan, Ji, Wei, Sung-Po
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): Naraghi, Ali
• Application Number:
  US12/005,130
• Publication Number:
  US 20090065861A1
• Time in Patent Office: 1,754 Days
• Field of Search: 257/428, 257/331, 257/339, 257/341, 257/E21.418
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain.

Claims

1. A semiconductor device formed on a semiconductor substrate, comprising:

a drain;

an epitaxial layer overlaying the drain; and

an active region comprising;

a body disposed in the epitaxial layer, having a body top surface;

a source embedded in the body, extending from the body top surface into the body;

a gate trench extending into the epitaxial layer;

a gate disposed in the gate trench;

an active region contact trench extending through the source and into the body;

an active region contact electrode disposed within the active region contact

trench;

wherein;

the body includes a thin body layer that separates the active region contact electrode from the drain and that has a dopant concentration that is substantially the same as the rest of the body;

thickness and dopant concentration of the body layer are such that in a reverse bias mode the layer of body region is substantially depleted, and in a forward bias mode the layer of body region is not depleted;

wherein a low injection diode is formed below a body/drain junction.

2. The semiconductor device of claim 1, wherein the thin layer of body region has a thickness range that is between 0.01˜

0.5 μ

m approximately.

3. The semiconductor device of claim 1, wherein the gate trench is a first gate trench;

and

the device further comprising a termination region comprising;

a second gate trench extending into the epitaxial layer;

a second gate disposed in the gate trench; and

a gate contact trench formed within the second gate.

4. The semiconductor device of claim 3, wherein the gate contact trench and the active region contact trench have approximately the same depth.

5. The semiconductor device of claim 3, wherein the active region contact trench has a different depth than the gate contact trench.

6. The semiconductor device of claim 1, wherein the active region contact trench has a non-uniform depth.

7. The semiconductor device of claim 1, wherein:

the active region contact trench has a first depth and a second depth;

the first depth is shallower than the second depth; and

a first contact opening corresponding to the first depth is wider than a second contact opening corresponding to the second depth.

8. The semiconductor device of claim 1, further comprising an anti-punch through implant disposed on a sidewall of the active region contact trench.

9. The semiconductor device of claim 1, further comprising a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

10. The semiconductor device of claim 1, further comprising an epitaxial layer profile tuning implant deposited under the active region contact trench.

11. The semiconductor device of claim 1, wherein the gate extends above the body top surface.

12. The semiconductor device of claim 1, wherein:

a thickness of the thin layer is measured from the bottom of the active region contact trench to the bottom of the body;

a depth of the active region contact trench is measured from the top surface of the semiconductor substrate to the bottom of the active region contact trench; and

the thickness of the thin layer of body region is substantially less than the depth of the active region contact trench.

13. The semiconductor device of claim 1, wherein:

the body layer is situated immediately adjacent to the bottom of the active contact trench.

14. A method of fabricating a semiconductor device, comprising:

forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;

depositing gate material in the gate trench;

forming a body;

forming a source;

forming an active region contact trench that extends through the source and into the body, and disposing a contact electrode within the active region contact trench;

wherein;

the body includes a thin body layer that separates the active

region contact electrode from the drain and that has a dopant concentration that is

substantially the same as the rest of the body;

thickness and dopant concentration of the body layer are such that in a reverse bias mode the layer of body region is substantially depleted, and in a forward bias mode, the layer of body region is not depleted;

wherein a low injection diode is formed below a body/drain junction.

15. The method of claim 14, wherein the gate trench is a first gate trench, and the method further comprising:

forming a second gate trench that extends into the epitaxial layer;

depositing gate material in the second gate trench; and

forming a gate contact trench within the gate.

16. The method of claim 15, wherein the gate contact trench and the active region contact trench have approximately the same depth.

17. The method of claim 15, wherein the active region contact trench has a different depth than the gate contact trench.

18. The method of claim 15, wherein the active region contact trench has a depth that is non-uniform.

19. The method of claim 14, further comprising depositing an anti-punch through implant on a sidewall of the active region contact trench.

20. The method of claim 14, further comprising depositing a blanket implant throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

21. The method of claim 14, further comprising depositing an epitaxial layer profile tuning implant under the active region contact trench, wherein the epitaxial layer profile tuning implant does not change epitaxial layer polarity.

22. The method of claim 14, further comprising:

forming a hard mask on the substrate prior to forming the gate trench;

removing the hard mask to leave a gate structure that extends above the body top surface.

23. The method of claim 14, wherein:

a thickness of the thin layer is measured from the bottom of the active region contact trench to the bottom of the body;

a depth of the active region contact trench is measured from the top surface of the semiconductor substrate to the bottom of the active region contact trench; and

the thickness of the thin layer of body region is substantially less than the depth of the active region contact trench.

24. The method of claim 14, wherein:

the body layer is situated immediately adjacent to the bottom of the active contact trench.