Memory element and semiconductor device, and method for manufacturing the same

• US 8,283,724 B2
• Filed: 02/20/2008
• Issued: 10/09/2012
• Est. Priority Date: 02/26/2007
• Status: Expired due to Fees

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hirakata, Yoshiharu
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): MCCALL SHEPARD, SONYA D
• Application Number:
  US12/034,334
• Publication Number:
  US 20080205132A1
• Time in Patent Office: 1,693 Days
• Field of Search: 257/E21.477, 257/350, 257/E27.103, 257E21645-E21658, 438/593
• US Class Current: 257/350
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition

Abstract

It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.

Claims

1. A memory element comprising:

a first conductive layer over and in contact with a first region of an insulating film;

a second conductive layer over and in contact with a second region of the insulating film; and

a conductive particle deposited between the first conductive layer and the second conductive layer, the conductive particle having a surface covered with an organic film,

wherein the first region is apart from the second region, and

wherein the first and second conductive layers are electrically connectable to each other at least through the conductive particle as a result in a writing operation of the memory element.

2. A memory element according to claim 1,

wherein the writing operation is performed by applying voltage between the first conductive layer and the second conductive layer.

3. A semiconductor device including a plurality of memory elements each of which comprises:

a first conductive layer and a second conductive layer that is beside the first conductive layer with an interval “

d”

;

a first conductive fine particle that overlaps the first conductive layer,

a second conductive fine particle interposed between the first conductive layer and the second conductive layer; and

a third conductive fine particle that overlaps the second conductive layer,

wherein the first conductive layer is over and in contact with an insulating film,

wherein the second conductive layer is over and in contact with the insulating film, and

wherein the first and second conductive layers are electrically connectable or electrically connected to each other at least through the second conductive fine particle as a result in applying voltage between the first conductive layer and the second conductive layer.

4. A semiconductor device according to claim 3,

wherein the interval “

d”

between the first conductive layer and the second conductive layer is smaller than a grain size of the second conductive fine particle.

5. A semiconductor device according to claim 3,

wherein a surface of the second conductive fine particle is covered with an organic film.

6. A semiconductor device according to claim 3,

wherein the first conductive layer is a bit line, and the second conductive layer is a word line.

7. A semiconductor device according to claim 3,

wherein the first conductive layer is a word line, and the second conductive layer is a bit line.

8. A semiconductor device according to claim 3, further comprising a thin film transistor,

wherein the thin film transistor is electrically connected to the first conductive layer or the second conductive layer.

9. A semiconductor device according to claim 3,

wherein an antenna and a power supply generating circuit are provided.

10. A semiconductor device including a memory element which comprises:

a first conductive layer and a second conductive layer that is beside the first conductive layer with an interval “

d”

;

a layer including;

a first conductive fine particle that overlaps the first conductive layer;

a second conductive fine particle that overlaps a region between the first conductive layer and the second conductive layer; and

a third conductive fine particle that overlaps the second conductive layer,

wherein the first conductive layer is over and in contact with an insulating film,

wherein the second conductive layer is over and in contact with the insulating film,

wherein the layer is in contact with a portion of the insulating film between the first conductive layer and the second conductive layer, and

wherein the first and second conductive layers are electrically connectable or electrically connected to each other at least through the second conductive fine particle.

11. A semiconductor device according to claim 10,

wherein the interval “

d”

between the first conductive layer and the second conductive layer is is smaller than a grain size of the second conductive fine particle.

12. A semiconductor device according to claim 10,

wherein a surface of the second conductive fine particle is covered with an organic film.

13. A semiconductor device according to claim 10,

wherein one of the first conductive layer and the second conductive layer is a bit line, and the other one of the first conductive layer and the second conductive layer is a word line.

14. A semiconductor device according to claim 10,

wherein the first conductive fine particle contacts the first conductive layer and the third conductive find particle contacts the second conductive layer.

15. A semiconductor device according to claim 10, further comprising a thin film transistor,

wherein the thin film transistor is electrically connected to one of the first conductive layer and the second conductive layer.

16. A semiconductor device according to claim 10,

wherein an antenna and a power supply generating circuit are provided.