Thermally balanced via
First Claim
1. A chip, comprising:
- a wafer portion having a first average coefficient of thermal expansion, wherein the wafer portion includes a via defined by a peripheral sidewall;
an insulating region having a second average coefficient of thermal expansion, wherein the insulating region is located within the via and covers at least a portion of the peripheral sidewall to a first thickness; and
a metallic region having a third average coefficient of thermal expansion, wherein the metallic region is located within the via and covers the insulating region to a second thickness;
wherein the first thickness and the second thickness are such that an average coefficient of thermal expansion of the combination of the insulating region and the metallic region substantially matches the first average coefficient of thermal expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.
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Accused Products
Abstract
A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.
325 Citations
20 Claims
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1. A chip, comprising:
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a wafer portion having a first average coefficient of thermal expansion, wherein the wafer portion includes a via defined by a peripheral sidewall; an insulating region having a second average coefficient of thermal expansion, wherein the insulating region is located within the via and covers at least a portion of the peripheral sidewall to a first thickness; and a metallic region having a third average coefficient of thermal expansion, wherein the metallic region is located within the via and covers the insulating region to a second thickness; wherein the first thickness and the second thickness are such that an average coefficient of thermal expansion of the combination of the insulating region and the metallic region substantially matches the first average coefficient of thermal expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A device comprising at least one chip, wherein the at least one chip comprises:
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a wafer portion having a first thermal expansion coefficient, wherein the wafer portion includes a via defined by a peripheral sidewall; an insulating region having a second thermal expansion coefficient, wherein the insulating region is located within the via and covers at least a portion of the peripheral sidewall to a first thickness; and a metallic region having a third thermal expansion coefficient, wherein the metallic region is located within the via and covers the insulation region to a second thickness; wherein the first thickness and the second thickness are such that an average coefficient of thermal expansion of the combination of the insulating region and the metallic region substantially matches the first thermal expansion coefficient of the wafer portion. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method of manufacturing a chip, wherein the chip comprises a wafer portion having a first average coefficient of thermal expansion, the method comprising:
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forming a via defined by a peripheral sidewall; forming an insulating region having a second average coefficient of thermal expansion, wherein the insulating region is located within the via and covers at least a portion of the peripheral sidewall to a first thickness; and forming a metallic region having a third average coefficient of thermal expansion, wherein the metallic region is located within the via and covers the insulating region to a second thickness; wherein the first thickness and the second thickness are such that an average coefficient of thermal expansion of the combination of the insulating region and the metallic region substantially matches the first average coefficient of thermal expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion. - View Dependent Claims (18, 19, 20)
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Specification