Amplifier circuit

• US 8,283,980 B2
• Filed: 09/25/2009
• Issued: 10/09/2012
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Arai, Tomoyuki, Kudo, Masahiro, Yamaura, Shinji
• Primary Examiner(s): Tso, Edward
• Assistant Examiner(s): BOATENG, ALEXIS ASIEDUA
• Application Number:
  US12/567,492
• Publication Number:
  US 20100039178A1
• Time in Patent Office: 1,110 Days
• Field of Search: 330/253, 330/254, 330/255, 330/260, 320/131, 320/141, 320/137, 320/140, 363/98, 363/16, 363/21.12, 363/21.15
• US Class Current: 330/253
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/456 A scaled replica of a transistor being present in an amplifier
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages

Abstract

An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.

Claims

1. An amplifier circuit comprising:

an amplifier unit including;

a gain compensation MOS transistor for compensating output characteristics of gain,

a linearity compensation MOS transistor for compensating output characteristics of linearity,

a source of the gain compensation MOS transistor for connecting with a drain of the linear characteristics compensation MOS transistor,

a drain of the gain compensation MOS transistor being set as an output, and

a gate of the linear characteristics compensation MOS transistor for inputting an input signal; and

a bias control circuit for controlling to apply predetermined current flowing through the drain to the source of the gain compensation MOS transistor, and to apply predetermined current flowing through the drain to the source of the linearity compensation MOS transistor.

2. The amplifier circuit of claim 1, wherein the bias control circuit controls to keep a value that subtracts a threshold voltage from the gate to source voltage of the linearity compensation MOS transistor.

3. The amplifier circuit of claim 1, wherein the bias control circuit controls to keep a current Ids flowing through the drain to the source of the gain compensation MOS transistor, or controls a current to keep a mutual conductance Gm.

4. The amplifier circuit of claim 1, wherein the bias control circuit controls a current so that the current flowing through the drain to the source of the linearity compensation MOS transistor is a reciprocal of current that passes between the drain and the source of the gain compensation MOS transistor.

5. The amplifier circuit of claim 1, wherein the amplifier unit includes a bypass unit for generating a part of current that passes between the drain and the source of the linearity compensation MOS transistor, and the current flowing through the drain to the source of the linear characteristics compensation MOS transistor is obtained by adding the current flowing through the drain to the source of the gain compensation MOS transistor and the current flowing through the bypass unit.

6. The amplifier circuit according to claim 1, wherein the bias control circuit includes a first current source for maintaining overdrive voltage Vod of the linearity compensation MOS transistor constant, and a second current source for maintaining mutual conductance Gm of the gain compensation MOS transistor constant.