Single device driver circuit to control three-dimensional memory element array

• US 8,284,589 B2
• Filed: 11/02/2010
• Issued: 10/09/2012
• Est. Priority Date: 08/20/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/938,028
• Publication Number:
  US 20120044733A1
• Time in Patent Office: 707 Days
• Field of Search: 365/148, 365/175
• US Class Current: 365/148
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.

Claims

1. A memory array, comprising:

an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and

a circuit comprising;

a bleeder diode having a first terminal coupled to a first bit line of the plurality of bit lines;

a bit line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a bit line decoder control lead; and

at least one first transistor of a first conductivity type having a gate coupled to the bit line decoder control lead, at least one of a source or a drain coupled to a bit line bias generator circuit, and the other one of the source or the drain coupled to the first bit line.

2. The array of claim 1, wherein a path to an unselected bias voltage source from a bit line bleeder diode is controlled by a same bit line decoder output that controls a path between a selected bias voltage source and the first bit line.

3. The array of claim 1, wherein the at least one first transistor comprises a single device driver configured to select the first bit line in response to signals from the bit line decoder and the bit line bias generator circuit.

4. The array of claim 1, wherein the bit line bleeder diode controller comprises a second transistor of a second conductivity type different from the first conductivity type, the second transistor having a gate, a drain, and a source, wherein one of the drain or the source of the second transistor is the bit line bleeder diode controller output lead coupled to the second terminal of the bleeder diode, the other one of the drain or the source of the second transistor is the bit line bleeder diode controller source lead coupled to the bias voltage source, and the gate of the second transistor is the bit line bleeder diode controller control input lead coupled to the bit line decoder control lead.

5. The array of claim 4, wherein the second transistor is an NMOS transistor, and the at least one first transistor is a PMOS transistor.

6. The array of claim 5, wherein the at least one first PMOS transistor comprises a plurality of first PMOS transistors, each first PMOS transistor having a gate coupled to the bit line decoder control lead, at least one of a source or a drain coupled to a different bit line bias generator circuit output, and the other one of the source or the drain coupled to a different one of a plurality of bit lines.

7. The array of claim 1, wherein:

the bleeder diode comprises a plurality of bleeder diodes each having a first terminal coupled to one of a plurality of bit lines; and

the bit line bleeder diode controller comprises a plurality of bit line bleeder diode controllers, wherein each of the plurality of bit line bleeder diode controllers has a control input lead, a source lead, and an output lead, the output lead of each of the plurality of bit line bleeder diode controllers is coupled to a second terminal of each of the plurality of bleeder diodes, the source lead of each of plurality of bit line bleeder diode controllers is coupled to a bias voltage source, and the control input lead of each of the plurality of bit line bleeder diode controllers is coupled to the bit line decoder control lead.

8. The array of claim 1, wherein:

the array comprises a monolithic three dimensional array of memory cell levels;

the bit line bias generator circuit and the bit line bleeder diode controller are located below the array of memory cell levels;

the bit line decoder is located in at least one level of the array of memory cell levels;

the bleeder diode is located in least one level or between two levels of the array of memory cell levels; and

the bit line bleeder diode controller is coupled to the bleeder diode by a zia and a special word line.

9. The array of claim 1, wherein the bleeder diode comprises a diode steering element.

10. The array of claim 9, wherein the bleeder diode comprises a dummy storage element connected in series with the diode steering element.