Serial data communication system and method

• US 8,284,823 B2
• Filed: 12/14/2006
• Issued: 10/09/2012
• Est. Priority Date: 01/03/2006
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Breitfuss, Klemens
• Primary Examiner(s): Vo, Don N
• Application Number:
  US12/159,966
• Publication Number:
  US 20090010371A1
• Time in Patent Office: 2,126 Days
• Field of Search: 375/219, 375/220, 375/222
• US Class Current: 375/219
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A serial data communication system (10) comprises—a local clock generation device (12) adapted for generating a clock signal (16) with a duty cycle depending on a control signal (18), and—a serial data communication control device (14) adapted for generating the control signal (18) depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal (20, 21) from the clock signal (16) received from the local clock generation device (12).

Claims

1. A serial data communication system comprising:

a local clock generation device adapted for generating a clock signal with a duty cycle depending on a control signal, and

a serial data communication control device adapted for generating the control signal depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal from the clock signal received from the local clock generation device.

2. The system of claim 1, wherein the local clock generation device is adapted to generate the clock signal with a predefined clock having a first duty cycle if the control signal comprises a first state and having a second duty cycle differing from the first duty cycle if the control signal comprises a second state.

3. The system of claim 1, wherein the serial data communication control device is adapted to generate a pulse of the receive clock signal triggered by the negative edge of a pulse of the clock signal when the control signal comprises a respective state.

4. The system according to claim 1, wherein it is adapted to transmit and receive data serially according to the RS232 standard.

5. The system of claim 1, wherein the local clock generation device includes:

an oscillator for generating a local high frequency clock signal, and

a clock generation circuit adapted for generating a clock signal from the local high frequency clock signal with a duty cycle depending on a control signal.

6. A serial data communication system comprising

a local clock generation device adapted for generating a clock signal with a duty cycle depending on a control signal,

a serial data communication control device adapted for generating the control signal depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal from the clock signal received from the local clock generation device, and

wherein the serial data communication control device is adapted to derive the transmit and receive clock signal from the clock signal received from the local clock generation device after the serial data signal was received for a predefined time.

7. A serial data communication control device comprising

a transmit and receive clock generation circuit coupled to an input of the serial data communication control device and adapted to generate a control signal from a receive data signal, received at the input, for controlling the generation of a clock signal,

data processing circuitry coupled to the input and configured and adapted to process data received from a serial data communication device, via the input, and data to be transmitted to a serial data communication device, and

wherein the transmit and receive clock generation circuit comprises a control signal generation circuit with a multiplexer, which receives a receive data signal and a constant signal on its input side, and a multiplexer control circuitry comprising a counter and being adapted for switching either of the input signals of the multiplexer to the multiplexer output as the control signal depending on the count of the counter.

8. A serial data communication method, comprising:

a local clock generation device generating a clock signal with a duty cycle depending on a control signal, and

a serial data communication control device generating the control signal depending on the receipt of a serial data signal and deriving a transmit and receive clock signal from the clock signal received from the local clock generation device.

9. A serial data communication system, comprising:

a serial data communication control device configured and arranged to;

receive and process data signals; and

generate a control signal, for generating a local clock signal depending on the receipt of a serial data signal, from the data signals;

an oscillator configured and arranged to generate a first clock cycle that is independent from the data signals; and

a local clock generation circuit configured and arranged to adjust the duty cycle of the first clock signal clock signal according to the control signals generated from the data signals to generate the local clock signal.

10. A serial data communication system, comprising:

a serial data communication control device configured and arranged to;

receive and process data signals; and

generate a control signal, for generating a local clock signal, from the data signals;

an oscillator configured and arranged to generate an first clock cycle that is independent from the data signals;

a local clock generation circuit configured and arranged to adjust the duty cycle of the first clock signal clock signal according to the control signals generated from the data signals to generate the local clock signal; and

wherein the serial data communication control device includes;

a multiplexor configured and arranged to receive the data signals on a first input and a logical 0 on a second input, a signal output from an output of the multiplexor being the control signal; and

a multiplexor control circuit configured and arranged to;

cause the second input of the multiplexor to be coupled to the output of the multiplexor in response to an accumulated number bits of the data signals being less than a predefined number of bits, the predefined number of bits being greater than 0; and

cause the first input of the multiplexor to be coupled to the output of the multiplexor in response to the accumulated number of bits of the data signals being greater than or equal to the predefined number of bits.