Serial concatenation of interleaved convolutional codes forming turbo-like codes

• US 8,284,833 B2
• Filed: 03/28/2011
• Issued: 10/09/2012
• Est. Priority Date: 05/18/2000
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Khandekar, Aamod, McEliece, Robert J., Jin, Hui
• Primary Examiner(s): HA, DAC V
• Application Number:
  US13/073,947
• Publication Number:
  US 20110264985A1
• Time in Patent Office: 561 Days
• Field of Search: 375/240, 375/240.24, 375/254, 375/285, 375/295, 375/296, 375/260, 714/755, 714/758, 714/800, 714/801, 714/804, 714/805
• US Class Current: 375/240
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1197 Irregular repeat-accumulate [IRA] codes
• CPC Class Codes: H03M 13/2939 using convolutional codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2972 Serial concatenation using convolutional component codes

Abstract

A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Claims

1. An apparatus for performing encoding operations, the apparatus comprising:

a first set of memory locations to store information bits;

a second set of memory locations to store parity bits;

a permutation module to read a bit from the first set of memory locations and combine the read bit to a bit in the second set of memory locations based on a corresponding index of the first set of memory locations and a corresponding index of the second set of memory locations; and

an accumulator to perform accumulation operations on the bits stored in the second set of memory locations,

wherein two or more memory locations of the first set of memory locations are read by the permutation module different times from one another.

2. The apparatus of claim 1, wherein the permutation module is configured to perform the combine operation to include performing mod-2 or exclusive-OR sum.

3. The apparatus of claim 2, wherein the permutation module is configured to perform the combining operation to further include writing the sum to the second set of memory locations based on a corresponding index.

4. The apparatus of claim 1, wherein the accumulator is configured to perform the accumulation operation to include a mod-2 or exclusive-OR sum of the bit stored in a prior index to a bit stored in a current index based on a corresponding index of the second set of memory locations.

5. The apparatus of claim 4, wherein the accumulator is configured to perform the accumulation operation to at least 2 consecutive indices of the second set of memory locations.

6. The apparatus of claim 1, wherein the permutation module further comprises a permutation information module to generate pairs of an index of the first set of memory locations and an index of the second set of memory locations.

7. The apparatus of claim 6, wherein at least one index of the second set of memory locations is used twice.

8. A method of performing encoding operations, the method comprising:

receiving a sequence of information bits from a first set of memory locations;

performing an encoding operation using the received sequence of information bits as an input, said encoding operation comprising;

reading a bit from the received sequence of information bits, and

combining the read bit to a bit in a second set of memory locations based on a corresponding index of the first set of memory locations for the received sequence of information bits and a corresponding index of the second set of memory locations; and

accumulating the bits in the second set of memory locations,

wherein two or more memory locations of the first set of memory locations are read by the permutation module different times from one another.

9. The method of claim 8, wherein performing the combine operation comprises performing mod-2 or exclusive-OR sum.

10. The method of claim 9, wherein performing the combine operation comprises writing the sum to the second set of memory locations based on a corresponding index.

11. The method of claim 8, wherein performing the accumulation operation comprises performing a mod-2 or exclusive-OR sum of the bit stored in a prior index to a bit stored in a current index based on a corresponding index of the second set of memory locations.

12. The method of claim 8, wherein the accumulation operation is performed to at least 2 consecutive indices of the second set of memory locations.

13. The method of claim 8, wherein the combining operation comprises generating pairs of an index of the first set of memory locations and an index of the second set of memory locations.

14. The method of claim 13, wherein at least one index of the second set of memory locations is used twice.