Techniques for processor/memory co-exploration at multiple abstraction levels

• US 8,285,535 B2
• Filed: 08/30/2010
• Issued: 10/09/2012
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Braun, Gunnar, Zorres, Olaf, Nohl, Achim, Hoffmann, Andreas
• Primary Examiner(s): PHAN, THAI Q
• Application Number:
  US12/871,884
• Publication Number:
  US 20100324880A1
• Time in Patent Office: 771 Days
• Field of Search: 703/2, 703/14, 716/4, 716/5, 711/100, 717/139
• US Class Current: 703/14
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.

Claims

1. A computer readable medium having embedded therein a set of application program interfaces (APIs) for use in one of a processor and memory co-simulations, said APIs comprising:

a first set of primitives operable for composition and sequencing to form a first communication protocol used with a functional level architecture description language (ADL) of a processor and a memory; and

a second set of primitives operable for composition and sequencing to form a second communication protocol used with a cycle-accurate level architecture description language (ADL) of said processor and said memory.

2. A computer readable medium as recited in claim 1, wherein said functional level ADL description of said processor and said memory is suitable for input to an automatic simulation generation tool, wherein an automatically generated functional processor/memory simulation model comprises a functional interface comprising said first set of primitives.

3. A computer readable medium as recited in claim 1, wherein said cycle-accurate ADL description of said processor and said memory is suitable for input to said automatic simulation generation tool, and wherein an automatically generated cycle-accurate processor/memory simulation model comprises a cycle-accurate interface comprising said second set of interfaces.

4. A computer readable medium as recited in claim 2, wherein said functional interface comprises a read primitive, and wherein memory access is performed immediately.

5. A computer readable medium as recited in claim 4, wherein said functional interface further comprises a write primitive, and wherein memory access is performed immediately.

6. A computer readable medium as recited in claim 2, wherein a memory access request is achieved with a single primitive in said first set of primitives using said functional interface, and wherein said single primitive is selected between a read primitive and a write primitive.

7. A computer readable medium as recited in claim 3, wherein said cycle-accurate interface comprises a request-based interface.

8. A computer readable medium as recited in claim 3, wherein said cycle-accurate interface comprises separate primitives in said second set of primitives for requesting and completing a memory access.

9. A processor and memory co-simulation method comprising:

generating a first set of primitives operable for composition and sequencing to form a first communication protocol used with a functional level architecture description language (ADL) of a processor and a memory;

generating a second set of primitives operable for composition and sequencing to form a second communication protocol used with a cycle-accurate level architecture description language (ADL) of said processor and said memory; and

storing said first and second set of primitives on a computing device readable medium as a set of application program interfaces (APIs).

10. The method according to claim 9, further comprising:

inputting said functional level ADL description of said processor and said memory to an automatic simulation generation tool to generate a functional one of a processor and memory simulation model including a functional interface comprising said first set of primitives.

11. The method according to claim 9, further comprising:

inputting said cycle-accurate ADL description of said processor and said memory to said automatic simulation generation tool to generate a cycle-accurate one of said processor and memory simulation model including a cycle-accurate interface comprising said second set of interfaces.

12. The method according to claim 10, wherein said functional interface comprises a read primitive, and wherein memory access is performed immediately.

13. The method according to claim 12, wherein said functional interface further comprises a write primitive, and wherein memory access is performed immediately.

14. The method according to claim 12, wherein a memory access request is achieved with a single primitive in said first set of primitives using said functional interface, and wherein said single primitive is selected between a read primitive and a write primitive.

15. The method according to claim 11, wherein said cycle-accurate interface comprises a request-based interface.

16. The method according to claim 11, wherein said cycle-accurate interface comprises separate primitives in said second set of primitives for requesting and completing a memory access.