SSD with improved bad block management

• US 8,285,919 B2
• Filed: 01/26/2010
• Issued: 10/09/2012
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Hangzhou Hualan Microelectronique Co., Ltd.
• Original Assignee: Initio Corporation (Hangzhou Hualan Microelectronique Co., Ltd.)
• Inventors: Luo, Jianjun, Tsu, ChuanJen
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/693,826
• Publication Number:
  US 20100122022A1
• Time in Patent Office: 987 Days
• Field of Search: 711/103, 711/114
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.

Claims

1. A memory controller, comprising:

a plurality of processors of a first type each configured to be coupled to at least one memory channel of a solid state memory device, each of the plurality of processors of the first type configured to determine a bad block rate of the at least one memory channel to which it is configured to be coupled; and

a processor of a second type in signal communication with each of the plurality of processors of the first type, the processor of the second type configured to;

receive the bad block data rates from each of the plurality of processors of the first type, and

report one of a total capacity or a bad block rate of the solid state memory device to a host device, the total capacity and the bad block rate of the solid state memory device based on the bad block rates received from each of the plurality of processors of the first type,

wherein the bad block rate of the solid state memory device is determined by calculating an average of the bad block rates received from each of the plurality of processors of the first type.

2. The memory controller of claim 1, wherein a first one of the plurality of processors of the first type is configured to be coupled to two memory channels and to determine a bad block rate of each of the two memory channels.

3. The memory controller of claim 2, wherein the first one of the plurality of processors of the first type is configured to sum together the bad block rates of the two memory channels.

4. The memory controller of claim 1, wherein each of the plurality of processors of the first type is configured to be coupled to a respective pair of memory channels and to determine a bad block rate of the respective pair of memory channels.

5. The memory controller of claim 4, wherein the bad block rate of the respective pair of memory channels is equal to a sum of the bad block rates of memory channels of the respective pair of memory channels.

6. The memory controller of claim 1, wherein the processor of the second type is configured to calculate the total memory capacity of the solid state memory device based on the bad block rates received from each of the plurality of processors of the first type.

7. The memory controller of claim 1, wherein each of the plurality of processors of the first type are configured to maintain a map of bad blocks for the at least one memory channel to which it is configured to be coupled.

8. A method of performing bad block management of a solid state drive (SSD), comprising:

identifying a first number of bad memory blocks of a first memory channel of the SSD at a first processor of a first type;

identifying a second number of bad memory blocks of a second memory channel of the SSD at a second processor of the first type;

calculating a bad block rate of the first memory channel at the first processor of the first type and a bad block rate of the second memory channel at the second processor of the first type, the bad block rate of the first memory channel based on the first number of bad memory blocks, the bad block rate of the second memory channel based on the second number of bad memory blocks;

determining a bad block rate of the SSD at a processor of a second type, the processor of the second type coupled to each of the processors of the first type; and

transmitting one of a memory capacity value of the SSD or the bad block rate of the SSD from the processor of the second type to a host device, the bad block rate of the SSD and the memory capacity value of the SSD based on the bad block rates calculated by the processors of the first type,

wherein the bad block rate of the SSD is equal to the greatest bad block rate calculated by the processors of the first type.

9. The method of claim 8, further comprising:

identifying a third number of bad memory blocks of a third memory channel of the SSD at the first processor of the first type;

calculating a bad block rate of the third memory channel at the first processor of the first type, the bad block rate of the third memory channel based on the third number of bad memory blocks; and

summing together the bad block rates of the first and third memory channels at the first processor of the first type.

10. The method of claim 9, further comprising:

identifying a fourth number of bad memory blocks of a fourth memory channel of the SSD at the second processor of the first type;

calculating a bad block rate of the fourth memory channel at the second processor of the first type, the bad block rate of the fourth memory channel based on the fourth number of bad memory blocks; and

summing together the bad block rates of the second and fourth memory channels at the second processor of the first type.

11. A system, comprising:

a memory controller coupled to a host device and to a solid state drive (SSD) having a plurality of memory channels, the memory controller including;

a plurality of processors of a first type each coupled to at least one of the plurality of memory channels of the SSD, each of the processors of the first type configured to;

identify a number of bad memory blocks in the memory channel to which it is coupled, and

determine a bad block rate of the memory channel to which it is coupled based on the number of bad memory blocks in the memory channel, and

a processor of a second type in signal communication with each of the plurality of processors of the first type, the processor of the second type configured to;

receive the bad block rates from each of the plurality of processors of the first type, and

report one of a total capacity or a bad block rate of the SSD to the host device, the total capacity and the bad block rate of the SSD based on the bad block rates received from each of the plurality of processors of the first type

wherein the bad block rate of the SSD is equal to the greatest bad block rate received from the plurality of processors of the first type.

12. The system of claim 11, wherein a first one of the plurality of processors of the first type is coupled to two memory channels and configured to determine a bad block rate of each of the two memory channels to which it is coupled.

13. The system of claim 12, wherein the first one of the plurality of processors of the first type is configured to sum together the bad block rates of the two memory channels to which it is coupled.

14. The system of claim 12, wherein each of the plurality of processors of the first type is coupled to a respective pair of memory channels and configured to determine a bad block rate of the respective pair of memory channels.

15. The system of claim 14, wherein the bad block rate of the respective pair of memory channels is equal to a sum of the bad block rates of each memory channel of the respective pair of memory channels.

16. A method of performing bad block management of a solid state drive (SSD), comprising:

identifying a first number of bad memory blocks of a first memory channel of the SSD at a first processor of a first type;

identifying a second number of bad memory blocks of a second memory channel of the SSD at a second processor of the first type;

calculating a bad block rate of the first memory channel at the first processor of the first type and a bad block rate of the second memory channel at the second processor of the first type, the bad block rate of the first memory channel based on the first number of bad memory blocks, the bad block rate of the second memory channel based on the second number of bad memory blocks;

determining a bad block rate of the SSD at a processor of a second type, the processor of the second type coupled to each of the processors of the first type; and

transmitting one of a memory capacity value of the SSD or the bad block rate of the SSD from the processor of the second type to a host device, the bad block rate of the SSD and the memory capacity value of the SSD based on the bad block rates calculated by the processors of the first type,

wherein the bad block rate of the SSD is equal to an average of the bad block rates calculated by the processors of the first type.

17. The method of claim 16, further comprising:

identifying a third number of bad memory blocks of a third memory channel of the SSD at the first processor of the first type;

calculating a bad block rate of the third memory channel at the first processor of the first type, the bad block rate of the third memory channel based on the third number of bad memory blocks; and

summing together the bad block rates of the first and third memory channels at the first processor of the first type.

18. The method of claim 17, further comprising:

identifying a fourth number of bad memory blocks of a fourth memory channel of the SSD at the second processor of the first type;

calculating a bad block rate of the fourth memory channel at the second processor of the first type, the bad block rate of the fourth memory channel based on the fourth number of bad memory blocks; and

summing together the bad block rates of the second and fourth memory channels at the second processor of the first type.