Independent link and bank selection

• US 8,285,960 B2
• Filed: 03/31/2011
• Issued: 10/09/2012
• Est. Priority Date: 09/30/2005
• Status: Expired due to Fees

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Oh, Hakjune, Kim, Jin-Ki
• Primary Examiner(s): NGUYEN, HIEP T
• Application Number:
  US13/077,122
• Publication Number:
  US 20110179245A1
• Time in Patent Office: 558 Days
• Field of Search: None
• US Class Current: 711/168
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Claims

1. An access controller for controlling access by at least two link controllers to at least two memory banks, the access controller comprising:

first invalid check logic for preventing simultaneous or overlapping access to a plurality of banks by the same link controller; and

second invalid check logic for preventing simultaneous or overlapping access to the same bank by a plurality of link controllers,

the access controller configured to produce control outputs in accordance with an output of the first invalid check logic and an output of the second invalid check logic.

2. The access controller of claim 1 further comprising:

bank select inputs for receiving a respective at least one bank select signal from each of the at least two link controllers.

3. The access controller of claim 2 wherein the bank select inputs for receiving a respective at least one bank select signal comprise:

for each link controller and bank combination, a respective bank select input for the link controller to select the bank.

4. The access controller of claim 3 wherein the second invalid check logic comprises, for each bank:

respective logic to detect when the respective bank select inputs for at least two link controller and bank combinations involving the bank are in a select state.

5. The access controller of claim 2 wherein the first invalid check logic comprising, for each link:

respective logic to detect when the respective bank select inputs for at least two link controller and bank combinations involving the link are in a select state.

6. The access controller of claim 1 further comprising:

an output holder for holding the control outputs to previous values

in the event of simultaneous or overlapping access to a plurality of banks by the same link controller, and

in the event of simultaneous or overlapping access the same bank by a plurality of link controllers.

7. The access controller of claim 1 further comprising:

bank selection logic for selecting a bank for read operation.

8. The access controller of claim 7 wherein the bank selection logic comprises:

for each bank, a respective combiner for combining a bank select signal for that bank and the output of the first invalid check logic.

9. The access controller of claim 1 wherein the control outputs comprise:

a respective enable for each link for writing, the enables for writing collectively being generated so as to prevent simultaneous or overlapping access to a plurality of banks by the same link controller; and

a respective enable for each bank for reading;

the enables for reading collectively being generated so as to prevent simultaneous or overlapping access to the same bank by a plurality of link controllers.

10. The access controller of claim 9 for use with links that comprise a first link and a second link, and for use with banks that comprise a first bank and a second bank.

11. A switching apparatus comprising:

an access controller for controlling access by a first link controller and a second link controller to a first memory bank and a second memory bank, the access controller comprising;

first invalid check logic for preventing simultaneous or overlapping access to both banks by the same link controller; and

second invalid check logic for preventing simultaneous or overlapping access to the same bank by both link controllers,

the access controller configured to produce control outputs in accordance with an output of the first invalid check logic and an output of the second invalid check logic;

wherein the control outputs comprise;

a respective enable for each link for writing, the enables for writing collectively being generated so as to prevent simultaneous or overlapping access to both banks by the same link controller; and

a respective enable for each bank for reading, the enables for reading collectively being generated so as to prevent simultaneous or overlapping access to the same bank by both link controllers;

the switching apparatus further comprising;

first switching logic comprising;

a first input for receiving a data input from the first link controller;

a second input for receiving the enable for writing for the first link;

a third input for receiving a data input from the second link controller;

a fourth input for receiving the enable for writing for the second link controller;

an output for outputting data to one of the first bank and the second bank; and

second switching logic comprising;

a first input for receiving a data input from the first bank;

a second input for receiving the enable for reading from the first bank;

a third input for receiving a data input from the second bank;

a fourth input for receiving the enable for reading from the second bank;

an output for outputting data read from the first or second bank.

12. A method of controlling access by at least two link controllers to a plurality of memory banks, the method comprising:

preventing simultaneous or overlapping access to a plurality of banks by the same link controller;

preventing simultaneous or overlapping access to the same bank by a plurality of link controllers;

producing control outputs in accordance with two preventing steps.

13. The method of claim 12 further comprising:

receiving a respective at least one bank select signal from each of the at least two link controllers.

14. The method of claim 13 wherein receiving a respective at least one bank select signal comprises:

for each link controller and bank combination, receiving a respective bank select input for the link controller to select the bank.

15. The method of claim 14 wherein preventing simultaneous or overlapping access to the same bank comprises, for each bank detecting when the respective bank select signals for at least two link controller and bank combinations involving the bank are in a select state.

16. The method of claim 14 wherein preventing simultaneous or overlapping access to a plurality of banks by the same link controller comprises, for each link:

detecting when the respective bank select signals for at least two link controller and bank combinations involving the link are in a select state.

17. The method of claim 12 further comprising:

holding the control outputs to previous values in the event of simultaneous or overlapping access to a plurality of banks by the same controller and in the event of simultaneous or overlapping access to the same bank by a plurality of link controllers.

18. The method of claim 12 further comprising selecting a bank for read operation.

19. The method of claim 12 wherein the control outputs comprise:

a respective enable for each link for writing, the enables for writing collectively being generated so as to prevent simultaneous or overlapping access to a plurality of banks by the same link controller;

a respective enable for each bank for reading, the enables for reading collectively being generated so as to prevent simultaneous or overlapping access to the same bank by a plurality of link controllers.

20. The method of claim 12 for use with links that comprise a first link and a second link, and for use with banks that comprise a first bank and a second bank.