Input/output device including a mechanism for accelerated error handling in multiple processor and multi-function systems

• US 8,286,027 B2
• Filed: 05/25/2010
• Issued: 10/09/2012
• Est. Priority Date: 05/25/2010
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Watkins, John E., Rodrigues, Elisa, Morshed, Abbas
• Primary Examiner(s): Lottich, Joshua P
• Application Number:
  US12/787,001
• Publication Number:
  US 20110296256A1
• Time in Patent Office: 868 Days
• Field of Search: 714/5.1, 714/5.11, 714/43, 714/49, 714/56
• US Class Current: 714/5.1
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing

Abstract

An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

Claims

1. An input/output (I/O) device comprising:

a host interface configured to receive and process a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex;

wherein the host interface includes an error handling unit having error logic configured to, as the transaction packets are received, determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage including a plurality of entries according to which processing unit and to which function of a plurality of functions each packet is associated;

wherein a given entry of a first portion of the plurality of entries corresponds to a respective function of the plurality of functions, and wherein a given entry of a second portion of the plurality of entries corresponds to a processor hierarchy associated with a respective processing unit;

wherein the error handling unit also includes;

an error processor configured to execute error processing instructions to access each entry of the storage that includes the information corresponding to any detected errors to determine any error processing operations based upon the information, and to generate and send one or more instruction operations, each corresponding to a particular error processing operation;

an error processing unit configured to execute the one or more instruction operations to perform the particular error processing operations.

2. The device as recited in claim 1, wherein the error processing operations include updating status registers of a plurality of groups of configuration space registers using one or more atomic read/modify/write operations, wherein each group of configuration space registers corresponds to one of the plurality of functions.

3. The device as recited in claim 2, wherein the status registers include one or more command status registers.

4. The device as recited in claim 2, wherein the status registers include one or more correctable and uncorrectable error status registers.

5. The device as recited in claim 2, wherein the status registers include one or more error header logs and respective associated first error pointer registers.

6. The device as recited in claim 2, wherein the status registers include one or more device status registers.

7. The device as recited in claim 1, wherein the error processing unit comprises a dedicated hardware unit configured to execute the instruction operations having a specific format.

8. The device as recited in claim 1, wherein the error processor is configured to perform additional tasks while the error processing unit executes the instruction operations.

9. A method comprising:

receiving and processing a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex;

as the transaction packets are received, an error handling unit determining whether each transaction packet has an error and storing information corresponding to any detected errors within a storage including a plurality of entries including a plurality of entries according to which processing unit and to which function of a plurality of functions each packet is associated;

wherein a given entry of a first portion of the plurality of entries corresponds to a respective function of the plurality of functions, and wherein a given entry of a second portion of the plurality of entries corresponds to a processor hierarchy associated with a respective processing unit;

subsequently processing the information corresponding to the detected errors by;

an error processor executing error processing instructions to access each entry of the storage that includes the information corresponding to any detected errors to determine any error processing operations based upon the information, and generating and sending one or more instruction operations, each corresponding to a particular error processing operation;

an error processing unit executing the one or more instruction operations to perform the particular error processing operations.

10. The method as recited in claim 9, wherein the error processing operations include updating status registers of a plurality of groups of configuration space registers using one or more atomic read/modify/write operations, wherein each group of configuration space registers corresponds to one of the plurality of functions.

11. The method as recited in claim 10, further comprising the error processing unit asserting an atomic operation indicator to prevent access to a specific status register during a read/modify/write operation of the specific status register.

12. The method as recited in claim 9, wherein the status registers include command status registers, correctable and uncorrectable error status, device status registers, error header logs, and first error pointer registers.

13. The method as recited in claim 9, further comprising the error processing unit notifying the error processor upon completion of the execution of the instruction operations dependent upon whether the error processor provided a notification signal to the error processing logic.

14. The method as recited in claim 13, further comprising the error processor performing additional tasks while the error processing unit executes the instruction operations.

15. A system comprising:

one or more processing units each configured to execute operating system software and one or more application device drivers; and

an input/output (I/O) device coupled to each of the one or more processing units via a respective communication link;

wherein the I/O device includes;

a host interface configured to receive and process a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex;

wherein the host interface includes an error handling unit having error logic configured to, as the transaction packets are received, determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage including a plurality of entries including a plurality of entries according to which processing unit and to which function of a plurality of functions each packet is associated;

wherein a given entry of a first portion of the plurality of entries corresponds to a respective function of the plurality of functions, and wherein a given entry of a second portion of the plurality of entries corresponds to a processor hierarchy associated with a respective processing unit;

wherein the error handling unit also includes;

an error processor configured to execute error processing instructions to access each entry of the storage that includes the information corresponding to any detected errors to determine any error processing operations based upon the information, and to generate and send one or more instruction operations, each corresponding to a particular error processing operation;

an error processing unit configured to execute the one or more instruction operations to perform the particular error processing operations.

16. The system as recited in claim 15, wherein the error processing operations include updating status registers of a plurality of groups of configuration space registers using one or more atomic read/modify/write operations, wherein each group of configuration space registers corresponds to one of the plurality of functions.

17. The system as recited in claim 16, wherein the error processing unit is configured to assert an atomic operation indicator to prevent access to a specific status register during a read/modify/write operation of the specific status register.

18. The system as recited in claim 16, wherein the status registers include command status registers, correctable and uncorrectable error status, device status registers, error header logs, and first error pointer registers.

19. A system comprising:

one or more processing units each configured to execute operating system software and one or more application device drivers; and

an input/output (I/O) device coupled to each of the one or more processing units via a respective communication link;

wherein the I/O device includes;

a host interface configured to receive and process a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex;

wherein the host interface includes an error handling unit having error logic configured to, as the transaction packets are received, determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage;

wherein the error handling unit also includes;

an error processor configured to execute error processing instructions to determine any error processing operations based upon the information and to generate and send one or more instruction operations, each corresponding to a particular error processing operation;

wherein the error processing operations include updating status registers of a plurality of groups of configuration space registers; and

wherein each instruction operation includes an opcode field, and address field, a data field, and a function field including an encoding of a number of functions for which the status register is to be modified; and

an error processing unit configured to execute the one or more instruction operations to perform the particular error processing operations.

20. A method comprising:

receiving and processing a plurality of transaction packets sent by a plurality of processing units, each processing unit corresponding to a respective root complex;

as the transaction packets are received, an error handling unit determining whether each transaction packet has an error and storing information corresponding to any detected errors;

subsequently processing the information corresponding to the detected errors by;

an error processor executing error processing instructions to determine any error processing operations based upon the information, and generating and sending one or more instruction operations, each corresponding to a particular error processing operation;

wherein the error processing operations include updating status registers of a plurality of groups of configuration space registers; and

wherein each instruction operation includes an opcode field, and address field, a data field, and a function field including an encoding of a number of functions for which the status register is to be modified; and

an error processing unit executing the one or more instruction operations to perform the particular error processing operations.