Integrated circuit testing module including signal shaping interface

• US 8,286,046 B2
• Filed: 06/16/2011
• Issued: 10/09/2012
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ong, Adrian E.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US13/162,112
• Publication Number:
  US 20110251819A1
• Time in Patent Office: 481 Days
• Field of Search: None
• US Class Current: 714/738
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.

Claims

1. A test module for coupling between a test equipment and a device to be tested, the device including an integrated circuit, comprising:

first components to communicate with the test equipment at a first frequency, the first components including one or more receiving components configured to receive test signals at the first frequency and to output information derived from the test signals;

one or more data generating components coupled to receive the information from the first components and configured to generate test data responsive to the information; and

second components to communicate with the device at a second frequency greater than the first frequency, the second components being configured to transmit the test data to the device.

2. The test module of claim 1, wherein the one or more data generating components are programmable to generate a variety of test patterns as the test data.

3. The test module of claim 1, wherein the first components include a clock manager, a command unit, a test control unit, and a test data interface.

4. The test module of claim 1, wherein the one or more data generating components store information selected from the group consisting of test codes, vectors, and patterns.

5. The test module of claim 1, wherein the one or more data generating components include an address generator, a pattern generation logic, write data logic, and data read logic.

6. The test module of claim 1, wherein the one or more data generating components include a test plan memory component configured to store at least a portion of a test plan, wherein the test plan include one or more of a sequence of tests and a series of data patterns associated with a sequence of tests to be sent to the device.

7. The test module of claim 6, wherein the sequence of tests include at least one of a group selected from:

an over voltage stress test, a synchronization test, a refresh related test, a worst-case-timing access test, and various combinations thereof.

8. The test module of claim 6, wherein the test plan includes conditional branches for determining which tests are to follow depending on whether a preceding test was successful or failed.

9. The test module of claim 1, wherein the one or more data generating components include a clock adjustment component configured to test at least one of a set-up time and a hold time of the device.

10. The test module of claim 1, wherein the second components include a clock driver, a command driver, an address driver, and a data interface.

11. The test module of claim 1, wherein the second components are further configured to receive test results from the device at the second frequency, and wherein the first components further includes output components to communicate to the test equipment at the first frequency information generated by the test module in response to the test results.

12. The test module of claim 1, wherein the first components includes an N-channel interface, and the second components includes an M-channel interface, wherein M is different from N.

13. The test module of claim 1, wherein the one or more data generating components includes a clock manager that is configured to receive at least one of a test clock at the first frequency and a PLL clock, the clock manger being further configured to generate one or more other clock signals at the second frequency.

14. The test module of claim 1, wherein the one or more data generating components include pattern generation logic configured to receive data from the first components and an address generator, and wherein the pattern generation logic generates address dependent test data based on inputs from the address generator.

15. The test module of claim 1, wherein the first components are configured to detachably couple to the test equipment.

16. The test module of claim 1, wherein the second component are configured to detachably couple to the device.

17. The test module of claim 1, wherein the test module is coupled to the device in a same package.

18. The test module of claim 1, wherein the device includes at least one of the group consisting of an application specific integrated circuit (ASIC), a processor, a microprocessor, a microcontroller, a field programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD).

19. The test module of claim 1, wherein the device includes at least one of the group consisting of an analog device, a module, a circuit board, and a memory device.

20. The test module of claim 1, wherein the device includes at least one of the group consisting of a system-in-package (SiP), package-in-package (PiP), or system-on-chip (SoC) and combinations thereof.

21. A method performed by a test module, comprising:

receiving signals having a first frequency from an automated testing equipment;

generating test signals within the test module responsive to the signals received from the automated testing equipment; and

sending the generated test signals to the integrated circuit at a second frequency faster than the first frequency.

22. The method of claim 21, wherein the signals received from the automated testing equipment include a signal to select at least one test plan, used to generate the test signals to be sent to the integrated circuit, from a test plan memory component including the at least one test plan.

23. The method of claim 22, wherein the at least one test plan may change based on results received from the integrated circuit in response to the generated test signals.