Multiplexed latching valves for microfluidic devices and processors

• US 8,286,665 B2
• Filed: 06/18/2010
• Issued: 10/16/2012
• Est. Priority Date: 03/22/2006
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Mathies, Richard A., Grover, William H., Jensen, Erik C.
• Primary Examiner(s): Schneider, Craig
• Assistant Examiner(s): CHAUDRY, ATIF H
• Application Number:
  US12/819,094
• Publication Number:
  US 20100252123A1
• Time in Patent Office: 851 Days
• Field of Search: 137/597, 137/829, 137/832, 137/907, 251/61.1, 251/331, 422/103, 235/201.ME
• US Class Current: 137/832
• CPC Class Codes: B01L 2200/12 Specific details about manufacturing devices
• CPC Class Codes: B01L 2300/0816 Cards, e.g. flat sample carriers usually with flow in two horizontal directions
• CPC Class Codes: B01L 2300/0887 Laminated structure
• CPC Class Codes: B01L 2400/0638 membrane valves, flap valves
• CPC Class Codes: B01L 3/5025 for parallel transport of multiple samples
• CPC Class Codes: B01L 3/502738 characterised by integrated valves microvalves F16K99/0001
• CPC Class Codes: F16K 2099/0071 with latching means
• CPC Class Codes: F16K 2099/0074 using photolithography, e.g. etching
• CPC Class Codes: F16K 2099/0084 Chemistry or biology, e.g. "lab-on-a-chip" technology
• CPC Class Codes: F16K 99/0001 Microvalves microdevices B81B1/00; manufacture or treatment of devices or systems in or on a substrate B81C1/00; microfluidic structures B01L3/5027; micropumps F04B19/006
• CPC Class Codes: F16K 99/0015 Diaphragm or membrane valves
• CPC Class Codes: F16K 99/0034 Operating means specially adapted for microvalves
• CPC Class Codes: F16K 99/0059 actuated by a pilot fluid
• CPC Class Codes: Y10T 137/2218 Means [e.g., valve] in control input
• CPC Class Codes: Y10T 137/3115 Gas pressure storage over or displacement of liquid
• CPC Class Codes: Y10T 137/5474 With heater
• CPC Class Codes: Y10T 137/87249 Multiple inlet with multiple outlet

Abstract

Membrane valves and latching valve structures for microfluidic devices are provided. A demultiplexer can be used to address the latching valve structures. The membrane valves and latching valve structures may be used to form pneumatic logic circuits, including processors.

Claims

1. A microfluidic logic circuit comprising:

an array of membrane valves, the array comprising a latching valve and a plurality of logic valves, wherein the logic valves are part of a single monolithic structure and wherein the latching valve and the logic valves are in fluid communication with each other to form a logic gate structure, and wherein the latching valve comprises;

a valve input configured to receive application of a pressure or a vacuum;

a valve control configured to receive application of a pressure, vacuum, or neither;

a valve output;

and a first normally-closed elastomer membrane configured such that the application of a pressure or a vacuum to the valve input and application of a pressure, a vacuum or neither to the valve control causes the membrane to deflect according to the following pneumatic logic;

2. The microfluidic logic circuit of claim 1 wherein the array of membrane valves includes two membrane valves configured to form an AND gate or an OR gate.

3. The microfluidic logic structure of claim 1 wherein the array of membrane valves is configured to form a NAND gate or an XOR gate.

4. The microfluidic logic circuit of claim 1 wherein the array of membrane valves is configured to form a buffer circuit.

5. The microfluidic logic circuit of claim 1 wherein the array of membrane valves is configured to form a ripple carrier adder.

6. The microfluidic logic circuit of claim 1 wherein the array of membrane valves includes two membrane valves connected in parallel.

7. The microfluidic logic circuit of claim 1 wherein the array of membrane valves includes two membrane valves connected in series.

8. The microfluidic logic circuit of claim 1 wherein the array of membrane valves is configured to form a full adder.