Three dimensional structure memory
First Claim
1. A method of making a circuit structure comprising:
- forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface;
forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate;
forming a dielectric layer over the first surface of at least one of the first and second unitary substrates, the dielectric layer having a stress of 5×
108 dynes/cm2 or less;
bonding the first surface of the first unitary substrate to one of the first surface and the second surface of the second unitary substrate;
thinning the second unitary substrate to form the second surface; and
,forming at least one vertical interconnection, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate.
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
315 Citations
94 Claims
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1. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; forming a dielectric layer over the first surface of at least one of the first and second unitary substrates, the dielectric layer having a stress of 5×
108 dynes/cm2 or less;bonding the first surface of the first unitary substrate to one of the first surface and the second surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; and
,forming at least one vertical interconnection, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 46, 47, 60, 67, 68, 81, 88)
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9. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; bonding the first surface of the first unitary substrate to the first surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; depositing a dielectric layer on the second surface of the second unitary substrate having a stress of about 5×
108 dynes/cm2 or less; and
,forming at least one vertical interconnection, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 48, 49, 61, 69, 70, 82, 89)
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17. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; bonding the first surface of the first unitary substrate to the first surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; and
,forming at least one vertical interconnection, wherein the said at least one vertical interconnection is formed in whole or in part from the first surface of the second unitary substrate, or in whole or in part from the second surface of the second unitary substrate, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (18, 19, 20, 21, 22, 23, 50, 51, 62, 71, 72, 83, 90)
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24. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface, and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; bonding the first surface of the first unitary substrate to one of the first surface and the second surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; depositing a dielectric layer on the second surface of the second unitary substrate having a stress of about 5×
108 dynes/cm2 or less; and
,forming at least one vertical interconnection, wherein said at least one vertical interconnection is formed in whole or in part from the first surface of the second unitary substrate, or in whole or in part from the second surface of the second unitary substrate, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (25, 26, 27, 28, 52, 53, 63, 73, 74, 84, 91)
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29. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface having one or more integrated circuits formed thereon; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; bonding the first surface of the first unitary substrate to the one of first surface and the second surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; and
,forming at least one vertical interconnection, wherein the said at least one vertical interconnection is formed in whole or in part from the first surface of the second unitary substrate, or in whole or in part from the second surface of the second unitary substrate, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (30, 31, 32, 33, 34, 54, 55, 64, 75, 76, 85, 92)
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35. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first unitary substrate; thinning the first unitary substrate to form the second surface thereof; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; thinning the second unitary substrate to form the second surface thereof; bonding the first surface of the second unitary substrate to the second surface of the first unitary substrate; and forming at least one vertical interconnection, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from said second unitary substrate. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 56, 57, 65, 77, 78, 86, 93)
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44. A method of making a circuit structure comprising:
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forming from a semiconductor wafer or portion thereof at least a first unitary substrate of a first type with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first unitary substrate; forming from a semiconductor wafer or portion thereof at least a first unitary substrate of a second type with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first unitary substrate of the second type; performing bonding of unitary substrate a surface of one of said unitary substrates to a surface of one of;
another of said unitary substrates, a second unitary substrate of said first type, and a second unitary substrate of said second type;thinning each of the first unitary substrate of the first type and the first unitary substrate of the second type by one of before performing bonding, thinning the unitary substrate to form the second surface of the unitary substrate while the first surface thereof is bonded to a support unitary substrate with an intervening release layer; and
, after performing bonding, thinning the unitary substrate to form the second surface of the unitary substrate; andforming at least one vertical interconnection that extends vertically through at least one of the first unitary substrate of the first type and the first unitary substrate of the second type, and forming a dielectric material having a stress of about 5×
108 dynes/cm2 or less isolating the vertical interconnection from a same unitary substrate. - View Dependent Claims (45, 58, 59, 66, 79, 80, 87, 94)
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Specification